Simple VME FMC Carrier 7 (SVEC7)
Project description
The FMC VME Carrier is an FMC carrier in VME64x format that can hold two FMC cards and an SFP connector. Unlike on the SVEC, where it is based on, the FMC mezzanine slots use high-pin count (HPC) connectors. This board is optimised for cost and will be usable with most of the FMC cards designed within the OHR project (e.g. ADC cards, Fine Delay).
TEMPLATE BELOW
SVEC V1 production board - block
diagram
Main Features
- VME64x interface
- Two Low-Pin Count FMC slots
- Vadj fixed to 2.5V
- No dedicated clock signals from Carrier to FMC (as only available on HPC pins and use LPC)
- FMC connectivity: all 34 differential pairs connected, 1 GTP transceiver with clock, 2 clock pairs, JTAG, I2C
- Xilinx FPGAs
- Application FPGA: Spartan-6 XC6SLX150T-3FGG900C
- Direct connection to all resources such as VME64x, memories and FMC connectors
- System FPGA: Spartan-6 XC6SLX9-2FTG256C
- Provides VME bootloader, early oscillator/PLL config
- Configuration Flash memory for both Main FPGA and Application FPGA configuration
- Application FPGA: Spartan-6 XC6SLX150T-3FGG900C
- FPGA configuration
- From SPI flash or via VME
- Clocking resources
- 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100 MHz (Silicon Labs Si570, freely usable)
- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
- 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
- 2x low-jitter frequency synthesizer/fanout (TI CDCM61004, fixed configuration, Fout=125 MHz, used by White Rabbit PTP core)
- On-board memories
- 2x 256 MByte (2 Gbit) DDR3 (16-bit bus, MT41J128M16JT-125)
- 1x 128 Mbit SPI flash for FPGA firmware storage (M25P128-VME6GB)
- 64kbit EEPROM connected for storing application parameters (24AA64T-I/MC)
- 1x I2C configuration EEPROM (24LC64)
- Miscellaneous
- On-board thermometer IC (DS18B20U+)
- Unique 64-bit identifier (DS18B20U+)
- Front panel
- 1x SFP port (White Rabbit compatible)
- 4x LEMO/SMC programmable I/Os capable of driving 3.3V @ 50 ohm
- 2x mini displayPort connectors for high-speed serial GTP links (not for video)
- 8x Programmable LED
- Reset push button
- Internal connectors
- VME P2 connector provides access to a Rear Transition Module
(compatible to
VFC)
- 40 user defined single ended (Vcco=2.5V) signals (or 20 LVDS pairs) connected to the Application FPGA
- 2x 125 MHz LVDS clocks provided to the RTM
- Xilinx-style JTAG connector
- Internal mini USB 2.0 High Speed connector for stand-alone applications (CP2103)
- VME P2 connector provides access to a Rear Transition Module
(compatible to
VFC)
- Optional features, check with vendor
- Internal 2 x SATA connector for stand-alone PCI Express connectivity (clock + data)
- Internal 4 x UFL connectors with low-jitter clock for FMC cards
- Internal additional USB 2.0 on 4-pin header (FT2232HL)
- Battery for secure storage of FPGA configuration data
- Stand-alone features
- External supply connector (3.3V, 5V) on internal SATA connector
- PCIe interface on internal SATA connector
- 10-layer PCB
Project information
- Official production documentation: EDA-02530
- Hardware manual (Janz Tec)
- CERN specific information
- Users
- Software
- Standard Gateware (and how to use it)
- Frequently Asked Questions
Releases
Latest:*
- Hardware: v3.0 -EDA-02530-V3-0
- Gateware: v3.0 - Gateware release 3.0
- Linux driver: see Software support for SVEC Project
All Gateware releases:* See the Releases page.
Contacts
Commercial producers
- none yet
General question about project
- Tomasz Wlostowski - CERN
- Erik van der Bij - CERN
Status
Date | Event |
---|---|
15-01-2019 | Discussion on how SVEC can handle data from dual 1GSPS ADC mezzanines. |
04-06-2019 | First specification to modify the SVEC written to request a company an offer. |
07-11-2019 | More detailed and advanced features such as variable Vadj for SVEC7 decided. |