Simple VME FMC Carrier 7 (SVEC7)

Project description

The FMC VME Carrier is an FMC carrier in VME64x format that can hold two FMC cards and an SFP connector. It's an evolution of the SVEC, but using a 7-Series FPGA (Kintex-7) and providing one HPC and one LPC connector with extra gigabit links to the one of the FMC slots. This board is optimised for cost and will be usable with most of the FMC cards designed within the OHR project (e.g. FMC ADC, Fine Delay, TDC, DIO, DDS).

SVEC V1 production board - block diagram

Main Features

• VME64x interface
• One Low-Pin Count FMC slot and one High Pin Count FMC slot
  • Programmable VAdj of 1.8, 2.5 or 3.3 V.
  • No dedicated clock signals from Carrier to FMC (as only available on HPC pins and use LPC)
  • FMC connectivity: all 34 differential pairs connected, 1 GTX transceiver with clock, 2 clock pairs, JTAG, I2C. Slot provides 4 GTXes connected using the HPC pins.
• Xilinx FPGAs
  • Application FPGA: Kintex-7 XC7K160T-1FBG676C
    • Direct connection to all resources such as memories and FMC connectors.
  • System FPGA: Spartan-6 XC6SLX9-2FTG256C
    • Provides a transparent bridge between the VME bus and the Application FPGA, reducing the required pin count in the AFPGA to handle the VME interface.
    • Provides VME bootloader, early oscillator/PLL config
    • Configuration Flash memory for both Main FPGA and Application FPGA configuration
• FPGA configuration
  • From SPI flash or via VME
• Clocking resources
  • 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100 MHz (Silicon Labs Si570, freely usable)
  • 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
  • 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
  • 2x low-jitter frequency synthesizer/fanout (TI CDCM61004, fixed configuration, Fout=125 MHz, used by White Rabbit PTP core)
• On-board memories
  • 1x SO-DIMM DDR3 module, 64-bit wide, no ECC, up to DDR3-1600.
  • 2x 256 Mbit SPI flash for FPGA firmware storage
  • 64kbit EEPROM connected for storing application parameters (24AA64T-I/MC)
  • 1x I2C configuration EEPROM (24LC64)
  • 1x unique MAC address EEPROM (AT24MAC402)
• Miscellaneous
  • On-board thermometer IC (DS18B20U+)
  • Unique 64-bit identifier (DS18B20U+)
• Front panel
  • 1x SFP port (White Rabbit compatible)
  • 4x LEMO/SMC programmable I/Os capable of driving 3.3V @ 50 ohm
  • 2x mini displayPort connectors for high-speed serial GTX links (not for video)
  • 8x Programmable LED
  • Reset push button
• Internal connectors
  • VME P2 connector provides access to a Rear Transition Module (compatible to VFC)
    • 40 user defined single ended (Vcco=2.5V) signals (or 20 LVDS pairs) connected to the Application FPGA
    • 2x 125 MHz LVDS clocks provided to the RTM
  • Xilinx-style JTAG connector
  • Internal mini USB 2.0 High Speed connector for stand-alone applications (FT2232H). Built-in USB JTAG.
• Optional features, check with vendor
  • Internal UFL connectors with low-jitter clock for FMC cards
  • Battery for secure storage of FPGA configuration data
  • Stand-alone features
    • External supply connector (3.3V, 5V) on internal SATA connector
• 10-layer PCB

Project information

Functional specification (and rationale for the redesign): svec7_tech_spec_20200406.pdf

The project is at design stage. More documentation will be published when the protypes become available.

Releases

Contacts

Commercial producers

• none yet

General question about project

• Tomasz Wlostowski - CERN
• Erik van der Bij - CERN

Status