| Page version | Author | Commit Message | Last updated | Format |
|---|---|---|---|---|
| fa22deb0 | Erik van der Bij | Status: |08-11-2020| Design ready. Will order three prototypes, likely ready by mid-March 2021. | | markdown | |
| eeaa5adb | Erik van der Bij | Changed FPGA from XC7K160T-1FBG676C to faster -2: XC7K160T-2FBG676C for which we have preferential pricing | markdown | |
| 36a10fbb | Erik van der Bij | Status: Not yet produced. Changes needed to be able to handle FMC ADC 1 GSPS | markdown | |
| 5dd02878 | Erik van der Bij | Status | markdown | |
| 0cd65a3f | Erik van der Bij | Update status: PCB design ready for review. | markdown | |
| 4817de2a | Tomasz Wlostowski | Update home | markdown | |
| bb928c1b | Tomasz Wlostowski | Update home | markdown | |
| 86fb3f20 | Tomasz Wlostowski | Update home | markdown | |
| 22a91bfc | Erik van der Bij | Status from MM message: chematics and layout both started. Review of SCH in 2 weeks, PCB in 4 weeks, prototypes ~begining of June. | markdown | |
| 492fd83d | Erik van der Bij | Added FPGA and memory type | markdown | |
| b964d40e | Erik van der Bij | Status | markdown | |
| b4f2462f | Erik van der Bij | erikvanderbij created page: home | markdown |