Ready for PCB layout review.

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Unstarted Issues (open and unassigned)

AFPGA Flash/AFPGA configuration issues
#57 minor

Ongoing Issues (open and assigned)

Perform test synthesis/P&R with the new pin assignment
#41 design
Documentation-related issues
#40 minor

Completed Issues (closed)

Bypass caps in FT4232
#60 minor
VAdj PSU should be controlled by the AFPGA
#59 major
Clocking: consider removing IC20 and SFP_CLK?
#56 design
Clocking: remove PLLFMC1_CLK/PLLFMC2_CLK.
#55 design
Clocking: Kintex-7 doesn't support LVPECL.
#54 major
IC4C: swapped Flash_MISO and Flash_MOSI lines.
#53 critical
Question about I/O expander connection
#52 RFC
Pulldowns missing on IOEXP_RCLK and IOEXP_RESET
#51 major
Do we need voltage translation to Vadj_FMC for FMC JTAG and I2C?
#50 RFC
Use CERN library components
#49 minor
CDCM61004 VCCVCO connection
#48 design RFC
IC8 VIN decoupling cap value
#47 RFC
LDO Soft-start time is set to 1s, is such a long time intentional?
#46 RFC
AFPGA_1V0: mixed-up LDO feedback dividers
#45 critical
DDR3 swapped
#38 critical
TPS74401RGWT bias
#37 critical
P1V0 considerations
#36 major
VP_0 and VN_0
#35 minor
sfpga: read dtack
#34 design
Add serial EEPROM that are preprogrammed with MAC address
#33 design

Ready for PCB layout review.

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