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Simple VME FMC Carrier 7 - SVEC7
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  • Simple VME FMC Carrier 7 - SVEC7
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  • Ready for PCB layout review.

Open
Milestone

Ready for PCB layout review.

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Learn more about issue boards, to keep track of issues in multiple lists, using labels, assignees, and milestones. If you’re missing something from issue boards, please create an issue on GitLab’s issue tracker.

  • Issues 23
  • Merge Requests 0
  • Participants 2
  • Labels 5
Unstarted Issues (open and unassigned)
1
  • AFPGA Flash/AFPGA configuration issues
    #57 minor
Ongoing Issues (open and assigned)
2
  • Perform test synthesis/P&R with the new pin assignment
    #41 design
  • Documentation-related issues
    #40 minor
Completed Issues (closed)
20
  • Bypass caps in FT4232
    #60 minor
  • VAdj PSU should be controlled by the AFPGA
    #59 major
  • Clocking: consider removing IC20 and SFP_CLK?
    #56 design
  • Clocking: remove PLLFMC1_CLK/PLLFMC2_CLK.
    #55 design
  • Clocking: Kintex-7 doesn't support LVPECL.
    #54 major
  • IC4C: swapped Flash_MISO and Flash_MOSI lines.
    #53 critical
  • Question about I/O expander connection
    #52 RFC
  • Pulldowns missing on IOEXP_RCLK and IOEXP_RESET
    #51 major
  • Do we need voltage translation to Vadj_FMC for FMC JTAG and I2C?
    #50 RFC
  • Use CERN library components
    #49 minor
  • CDCM61004 VCCVCO connection
    #48 designRFC
  • IC8 VIN decoupling cap value
    #47 RFC
  • LDO Soft-start time is set to 1s, is such a long time intentional?
    #46 RFC
  • AFPGA_1V0: mixed-up LDO feedback dividers
    #45 critical
  • DDR3 swapped
    #38 critical
  • TPS74401RGWT bias
    #37 critical
  • P1V0 considerations
    #36 major
  • VP_0 and VN_0
    #35 minor
  • sfpga: read dtack
    #34 design
  • Add serial EEPROM that are preprogrammed with MAC address
    #33 design
86% complete
86%
Start date
No start date
None
Due date
No due date
23
Issues 23 New issue
Open: 3 Closed: 20
Time tracking
0
Merge requests 0
Open: 0 Closed: 0 Merged: 0
Reference: project/svec7%"Ready for PCB layout review."