Ready for PCB layout review.
Completed Issues (closed)
- Bypass caps in FT4232
- VAdj PSU should be controlled by the AFPGA
- Clocking: consider removing IC20 and SFP_CLK?
- Clocking: remove PLLFMC1_CLK/PLLFMC2_CLK.
- Clocking: Kintex-7 doesn't support LVPECL.
- IC4C: swapped Flash_MISO and Flash_MOSI lines.
- Question about I/O expander connection
- Pulldowns missing on IOEXP_RCLK and IOEXP_RESET
- Do we need voltage translation to Vadj_FMC for FMC JTAG and I2C?
- Use CERN library components
- CDCM61004 VCCVCO connection
- IC8 VIN decoupling cap value
- LDO Soft-start time is set to 1s, is such a long time intentional?
- AFPGA_1V0: mixed-up LDO feedback dividers
- DDR3 swapped
- TPS74401RGWT bias
- P1V0 considerations
- VP_0 and VN_0
- sfpga: read dtack
- Add serial EEPROM that are preprogrammed with MAC address