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Simple VME FMC Carrier 7 - SVEC7
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  • Simple VME FMC Carrier 7 - SVEC7
  • Issues

  • Open 12
  • Closed 85
  • All 97
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  • Priority Created date Last updated Milestone Due date Popularity Label priority
  • Clocking: Kintex-7 doesn't support LVPECL.
    #54 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   major
    • CLOSED
    • 2
    updated Sep 24, 2020
  • FMC DP should be length matched
    #90 · opened Jul 06, 2020 by Grzegorz Daniluk   Ready for V1 prototype   design minor
    • CLOSED
    • 4
    updated Aug 20, 2020
  • update copyright in schematics and license to CERN OHL v2
    #87 · opened Jul 06, 2020 by Grzegorz Daniluk   Ready for V1 prototype   minor
    • CLOSED
    • 1
    updated Aug 13, 2020
  • [L1] WR_MODDEV0..2, WR_TXDISABLE, WR_TXFAULT vias don't have to be so close together
    #79 · opened Jul 06, 2020 by Grzegorz Daniluk
    • CLOSED
    • 1
    updated Aug 13, 2020
  • Diff pairs impedance
    #96 · opened Jul 08, 2020 by Evangelia Gousiou   Ready for V1 prototype   design major
    • CLOSED
    • 3
    updated Aug 13, 2020
  • V3 - mini displayPort connector obsolete (J5, J9)
    #13 · opened Mar 16, 2020 by Filip Świtakowski
    • CLOSED
    • 5
    updated Aug 13, 2020
  • AFPGA can't be programmed from SFPGA on-the-fly
    #58 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for V1 prototype   critical
    • CLOSED
    • 1
    updated Jul 22, 2020
  • No heatsink on K7
    #69 · opened Jun 01, 2020 by Paweł Kulik   Ready for V1 prototype
    • CLOSED
    • 2
    updated Jul 22, 2020
  • FMC LA should be length matched
    #89 · opened Jul 06, 2020 by Grzegorz Daniluk   Ready for V1 prototype   design major
    • CLOSED
    • 3
    updated Jul 22, 2020
  • Project name
    #93 · opened Jul 08, 2020 by Evangelia Gousiou   Ready for V1 prototype   minor
    • CLOSED
    • 3
    updated Jul 22, 2020
  • Don't we want cutouts below FMCs like on SPEC or DI/OT System Board?
    #86 · opened Jul 06, 2020 by Grzegorz Daniluk
    • CLOSED
    • 3
    updated Jul 21, 2020
  • FMC front panel mounting holes should be connected to chassis GND (not signal GND)
    #92 · opened Jul 06, 2020 by Grzegorz Daniluk
    • CLOSED
    • 1
    updated Jul 19, 2020
  • Use CERN library components
    #49 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   minor
    • CLOSED
    • 2
    updated Jul 19, 2020
  • Crosstalk
    #97 · opened Jul 08, 2020 by Evangelia Gousiou   Ready for V1 prototype   minor
    • CLOSED
    • 4
    updated Jul 19, 2020
  • PCB version
    #94 · opened Jul 08, 2020 by Evangelia Gousiou   Ready for V1 prototype   design major
    • CLOSED
    • 3
    updated Jul 19, 2020
  • Having Spartan-6 as SFPGA could again cause part obsolescence problem in a few years, why not Spartan-7 or Artix-7?
    #85 · opened Jul 06, 2020 by Grzegorz Daniluk
    • 2
    updated Jul 17, 2020
  • many traces have over-complicated routing, crossing layers multiple times
    #88 · opened Jul 06, 2020 by Grzegorz Daniluk
    • 2
    updated Jul 17, 2020
  • FMC DP lines could be routed with soft corners for better SI
    #91 · opened Jul 06, 2020 by Grzegorz Daniluk
    • CLOSED
    • 1
    updated Jul 12, 2020
  • Silkscreen
    #95 · opened Jul 08, 2020 by Evangelia Gousiou
    • CLOSED
    • 1
    updated Jul 12, 2020
  • [L8] SFPGA-AFPGA link (SFPGA_TX_xx, SFPGA_RX_xx) crosses split power plane in L9
    #81 · opened Jul 06, 2020 by Grzegorz Daniluk
    • 1
    updated Jul 12, 2020
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