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Simple VME FMC Carrier 7 - SVEC7
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Simple VME FMC Carrier 7 - SVEC7
Issues
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12
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85
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Missing capacitors - SFPGA
#23
· opened
Mar 16, 2020
by
Filip Świtakowski
CLOSED
1
updated
Mar 20, 2020
FMC LA should be length matched
#89
· opened
Jul 06, 2020
by
Grzegorz Daniluk
Ready for V1 prototype
design
major
CLOSED
3
updated
Jul 22, 2020
[TSilk] "PCIe data" and "PCIe clock & SUPPLY" refers to what exactly? The connector above provides only power.
#76
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[TSilk] Add text "HPC" and "LPC" to indicate the type of FMC slot.
#77
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[L10] X:7217mil Y:6406mil - P1V0 polygon creates multiple acid traps
#84
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
Flash memory
#6
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
1
updated
Mar 01, 2020
Remove J1 and J16 (stand-alone power port)
#3
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
3
updated
Jul 02, 2020
Remove the discrete DDR chips (IC28, IC4)
#4
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
1
updated
Feb 10, 2020
Schematics conventions
#29
· opened
Mar 17, 2020
by
Filip Świtakowski
CLOSED
1
updated
Mar 19, 2020
PCB version
#94
· opened
Jul 08, 2020
by
Evangelia Gousiou
Ready for V1 prototype
design
major
CLOSED
3
updated
Jul 19, 2020
sfpga: read dtack
#34
· opened
Apr 07, 2020
by
Tristan Gingold
Ready for PCB layout review.
design
CLOSED
1
4
updated
Jul 12, 2020
[L4] duplicate P5V_VME polygon on one more layer?
#80
· opened
Jul 06, 2020
by
Grzegorz Daniluk
0
updated
Jul 06, 2020
Missing PU/PD resistors
#24
· opened
Mar 16, 2020
by
Filip Świtakowski
CLOSED
1
updated
Mar 19, 2020
Having Spartan-6 as SFPGA could again cause part obsolescence problem in a few years, why not Spartan-7 or Artix-7?
#85
· opened
Jul 06, 2020
by
Grzegorz Daniluk
2
updated
Jul 17, 2020
[L10] X:5445mil Y:3854mil - possible acid trap
#82
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[L10] X:5647mil Y:4087mil - sumoptimal polygon shape around P3V3_FMC pad
#83
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
Don't we want cutouts below FMCs like on SPEC or DI/OT System Board?
#86
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
3
updated
Jul 21, 2020
update copyright in schematics and license to CERN OHL v2
#87
· opened
Jul 06, 2020
by
Grzegorz Daniluk
Ready for V1 prototype
minor
CLOSED
1
updated
Aug 13, 2020
FMC DP should be length matched
#90
· opened
Jul 06, 2020
by
Grzegorz Daniluk
Ready for V1 prototype
design
minor
CLOSED
4
updated
Aug 20, 2020
Memory symbols IC24A and IC24B are swapped
#30
· opened
Mar 17, 2020
by
Filip Świtakowski
CLOSED
1
updated
Mar 19, 2020
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