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Simple VME FMC Carrier 7 - SVEC7
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Simple VME FMC Carrier 7 - SVEC7
Issues
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12
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85
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Power supply
3 of 3 tasks completed
#9
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
7
updated
Mar 23, 2020
Vadj_FMC
#17
· opened
Mar 16, 2020
by
Filip Świtakowski
CLOSED
3
updated
Mar 23, 2020
Change THT caps to SMD
#28
· opened
Mar 17, 2020
by
Filip Świtakowski
CLOSED
3
updated
Mar 20, 2020
Missing capacitors - SFPGA
#23
· opened
Mar 16, 2020
by
Filip Świtakowski
CLOSED
1
updated
Mar 20, 2020
Unconnected Signals
#22
· opened
Mar 16, 2020
by
Filip Świtakowski
CLOSED
1
updated
Mar 20, 2020
Missing MGTAVTT_P1V2 power supply
#21
· opened
Mar 16, 2020
by
Filip Świtakowski
CLOSED
1
updated
Mar 20, 2020
MGT power
#20
· opened
Mar 16, 2020
by
Filip Świtakowski
CLOSED
1
updated
Mar 20, 2020
Add TP to Vadj_FMC
#19
· opened
Mar 16, 2020
by
Filip Świtakowski
CLOSED
1
updated
Mar 20, 2020
Missing PU/PD resistors
#24
· opened
Mar 16, 2020
by
Filip Świtakowski
CLOSED
1
updated
Mar 19, 2020
Schematics conventions
#29
· opened
Mar 17, 2020
by
Filip Świtakowski
CLOSED
1
updated
Mar 19, 2020
Memory symbols IC24A and IC24B are swapped
#30
· opened
Mar 17, 2020
by
Filip Świtakowski
CLOSED
1
updated
Mar 19, 2020
Fuse - P3V3_FMC
#32
· opened
Mar 17, 2020
by
Filip Świtakowski
CLOSED
1
updated
Mar 19, 2020
Q4 ang Q5
#26
· opened
Mar 17, 2020
by
Filip Świtakowski
CLOSED
0
updated
Mar 17, 2020
Kintex Vadj
#18
· opened
Mar 16, 2020
by
Filip Świtakowski
CLOSED
1
updated
Mar 16, 2020
Missing Differential pair labels
#15
· opened
Mar 16, 2020
by
Filip Świtakowski
CLOSED
1
updated
Mar 16, 2020
NON-CERN components
#14
· opened
Mar 16, 2020
by
Filip Świtakowski
CLOSED
1
updated
Mar 16, 2020
Flash memory
#6
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
1
updated
Mar 01, 2020
Change the FPGA to XC7K160T-2FBG676
#1
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
1
updated
Feb 25, 2020
Use FT2232 instead of CP2103
#2
· opened
Feb 05, 2020
by
Mikolaj Sowinski
design
CLOSED
2
updated
Feb 25, 2020
FPGA Bank Assignment
#12
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
0
updated
Feb 19, 2020
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