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Simple VME FMC Carrier 7 - SVEC7
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Simple VME FMC Carrier 7 - SVEC7
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12
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Pulldowns missing on IOEXP_RCLK and IOEXP_RESET
#51
· opened
Apr 20, 2020
by
Tomasz Wlostowski
Ready for PCB layout review.
major
CLOSED
1
updated
Apr 27, 2020
Bypass caps in FT4232
#60
· opened
Apr 20, 2020
by
Tomasz Wlostowski
Ready for PCB layout review.
minor
CLOSED
1
updated
Apr 27, 2020
Clocking: remove PLLFMC1_CLK/PLLFMC2_CLK.
#55
· opened
Apr 20, 2020
by
Tomasz Wlostowski
Ready for PCB layout review.
design
CLOSED
1
updated
Apr 27, 2020
Use CERN library components
#49
· opened
Apr 20, 2020
by
Tomasz Wlostowski
Ready for PCB layout review.
minor
CLOSED
2
updated
Jul 19, 2020
No matched net length within differential pair
#64
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
FMC front panel mounting holes should be connected to chassis GND (not signal GND)
#92
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 19, 2020
OHWR license on PCB should be newer
#70
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
IC8 doesn't have thermal relief vias
#75
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 02, 2020
Change name of the board in silkscreen
#71
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 02, 2020
DDR reference plane continuity
#74
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
No heatsink on K7
#69
· opened
Jun 01, 2020
by
Paweł Kulik
Ready for V1 prototype
CLOSED
2
updated
Jul 22, 2020
DRC check
#62
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
8 silkscreen strings are outside of the board
#72
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
Matched length between DDR address and data
#65
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
Stackup table
1 of 2 tasks completed
#67
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
0
updated
Jun 04, 2020
Vias under SMD pads should be unmasked
#66
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 02, 2020
Reference plane continuity for differential pairs problems
10 of 10 tasks completed
#73
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
Clocking: Kintex-7 doesn't support LVPECL.
#54
· opened
Apr 20, 2020
by
Tomasz Wlostowski
Ready for PCB layout review.
major
CLOSED
2
updated
Sep 24, 2020
V3 - mini displayPort connector obsolete (J5, J9)
#13
· opened
Mar 16, 2020
by
Filip Świtakowski
CLOSED
5
updated
Aug 13, 2020
[L1] J16 unnecessary, unused traces from S2, S3 pad
#78
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
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