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Simple VME FMC Carrier 7 - SVEC7
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Simple VME FMC Carrier 7 - SVEC7
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[TSilk] "PCIe data" and "PCIe clock & SUPPLY" refers to what exactly? The connector above provides only power.
#76
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[L10] X:5647mil Y:4087mil - sumoptimal polygon shape around P3V3_FMC pad
#83
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[L10] X:5445mil Y:3854mil - possible acid trap
#82
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[L1] J16 unnecessary, unused traces from S2, S3 pad
#78
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
Remove J1 and J16 (stand-alone power port)
#3
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
3
updated
Jul 02, 2020
Stackup table
1 of 2 tasks completed
#67
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
0
updated
Jun 04, 2020
Reference plane continuity for differential pairs problems
10 of 10 tasks completed
#73
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
DRC check
#62
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
DDR reference plane continuity
#74
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
OHWR license on PCB should be newer
#70
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
Matched length between DDR address and data
#65
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
No matched net length within differential pair
#64
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
8 silkscreen strings are outside of the board
#72
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
Vias under SMD pads should be unmasked
#66
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 02, 2020
Change name of the board in silkscreen
#71
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 02, 2020
IC8 doesn't have thermal relief vias
#75
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 02, 2020
No buffers on VME P2 lines?
#44
· opened
Apr 20, 2020
by
Tomasz Wlostowski
RFC
CLOSED
4
updated
Apr 28, 2020
Pull up the DDR3_RESET_N instead of down?
#42
· opened
Apr 20, 2020
by
Tomasz Wlostowski
minor
CLOSED
2
updated
Apr 27, 2020
LDO Soft-start time is set to 1s, is such a long time intentional?
#46
· opened
Apr 20, 2020
by
Tomasz Wlostowski
Ready for PCB layout review.
RFC
CLOSED
1
updated
Apr 27, 2020
Pulldowns missing on IOEXP_RCLK and IOEXP_RESET
#51
· opened
Apr 20, 2020
by
Tomasz Wlostowski
Ready for PCB layout review.
major
CLOSED
1
updated
Apr 27, 2020
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