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Simple VME FMC Carrier 7 - SVEC7
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Simple VME FMC Carrier 7 - SVEC7
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12
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many traces have over-complicated routing, crossing layers multiple times
#88
· opened
Jul 06, 2020
by
Grzegorz Daniluk
2
updated
Jul 17, 2020
update copyright in schematics and license to CERN OHL v2
#87
· opened
Jul 06, 2020
by
Grzegorz Daniluk
Ready for V1 prototype
minor
CLOSED
1
updated
Aug 13, 2020
Don't we want cutouts below FMCs like on SPEC or DI/OT System Board?
#86
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
3
updated
Jul 21, 2020
Having Spartan-6 as SFPGA could again cause part obsolescence problem in a few years, why not Spartan-7 or Artix-7?
#85
· opened
Jul 06, 2020
by
Grzegorz Daniluk
2
updated
Jul 17, 2020
[L10] X:7217mil Y:6406mil - P1V0 polygon creates multiple acid traps
#84
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[L10] X:5647mil Y:4087mil - sumoptimal polygon shape around P3V3_FMC pad
#83
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[L10] X:5445mil Y:3854mil - possible acid trap
#82
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[L8] SFPGA-AFPGA link (SFPGA_TX_xx, SFPGA_RX_xx) crosses split power plane in L9
#81
· opened
Jul 06, 2020
by
Grzegorz Daniluk
1
updated
Jul 12, 2020
[L4] duplicate P5V_VME polygon on one more layer?
#80
· opened
Jul 06, 2020
by
Grzegorz Daniluk
0
updated
Jul 06, 2020
[L1] WR_MODDEV0..2, WR_TXDISABLE, WR_TXFAULT vias don't have to be so close together
#79
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Aug 13, 2020
[L1] J16 unnecessary, unused traces from S2, S3 pad
#78
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[TSilk] Add text "HPC" and "LPC" to indicate the type of FMC slot.
#77
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[TSilk] "PCIe data" and "PCIe clock & SUPPLY" refers to what exactly? The connector above provides only power.
#76
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
IC8 doesn't have thermal relief vias
#75
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 02, 2020
DDR reference plane continuity
#74
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
Reference plane continuity for differential pairs problems
10 of 10 tasks completed
#73
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
8 silkscreen strings are outside of the board
#72
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
Change name of the board in silkscreen
#71
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 02, 2020
OHWR license on PCB should be newer
#70
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
No heatsink on K7
#69
· opened
Jun 01, 2020
by
Paweł Kulik
Ready for V1 prototype
CLOSED
2
updated
Jul 22, 2020
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