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Simple VME FMC Carrier 7 - SVEC7
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Simple VME FMC Carrier 7 - SVEC7
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12
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[TSilk] Add text "HPC" and "LPC" to indicate the type of FMC slot.
#77
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[TSilk] "PCIe data" and "PCIe clock & SUPPLY" refers to what exactly? The connector above provides only power.
#76
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
IC8 doesn't have thermal relief vias
#75
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 02, 2020
DDR reference plane continuity
#74
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
Reference plane continuity for differential pairs problems
10 of 10 tasks completed
#73
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
8 silkscreen strings are outside of the board
#72
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
Change name of the board in silkscreen
#71
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 02, 2020
OHWR license on PCB should be newer
#70
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
No heatsink on K7
#69
· opened
Jun 01, 2020
by
Paweł Kulik
Ready for V1 prototype
CLOSED
2
updated
Jul 22, 2020
No copper balancing
#68
· opened
Jun 01, 2020
by
Paweł Kulik
0
updated
Jun 01, 2020
Stackup table
1 of 2 tasks completed
#67
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
0
updated
Jun 04, 2020
Vias under SMD pads should be unmasked
#66
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 02, 2020
Matched length between DDR address and data
#65
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
No matched net length within differential pair
#64
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
DiffPairsRouting rule
#63
· opened
Jun 01, 2020
by
Paweł Kulik
1
updated
Jun 02, 2020
DRC check
#62
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
Generate FPGA pinout
#61
· opened
Apr 22, 2020
by
Mikolaj Sowinski
1
updated
Jun 01, 2020
Bypass caps in FT4232
#60
· opened
Apr 20, 2020
by
Tomasz Wlostowski
Ready for PCB layout review.
minor
CLOSED
1
updated
Apr 27, 2020
VAdj PSU should be controlled by the AFPGA
#59
· opened
Apr 20, 2020
by
Tomasz Wlostowski
Ready for PCB layout review.
major
CLOSED
1
updated
Apr 27, 2020
AFPGA can't be programmed from SFPGA on-the-fly
#58
· opened
Apr 20, 2020
by
Tomasz Wlostowski
Ready for V1 prototype
critical
CLOSED
1
updated
Jul 22, 2020
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