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Simple VME FMC Carrier 7 - SVEC7
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  • Simple VME FMC Carrier 7 - SVEC7
  • Issues

  • Open 3
  • Closed 20
  • All 23
New issue
Recent searches
  • Priority Created date Last updated Milestone Due date Popularity Label priority
  • Bypass caps in FT4232
    #60 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   minor
    • CLOSED
    • 1
    updated Apr 27, 2020
  • VAdj PSU should be controlled by the AFPGA
    #59 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   major
    • CLOSED
    • 1
    updated Apr 27, 2020
  • AFPGA Flash/AFPGA configuration issues
    #57 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   minor
    • 3
    updated Apr 27, 2020
  • Clocking: consider removing IC20 and SFP_CLK?
    #56 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   design
    • CLOSED
    • 1
    updated Apr 27, 2020
  • Clocking: remove PLLFMC1_CLK/PLLFMC2_CLK.
    #55 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   design
    • CLOSED
    • 1
    updated Apr 27, 2020
  • Clocking: Kintex-7 doesn't support LVPECL.
    #54 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   major
    • CLOSED
    • 2
    updated Sep 24, 2020
  • IC4C: swapped Flash_MISO and Flash_MOSI lines.
    #53 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   critical
    • CLOSED
    • 1
    updated Apr 27, 2020
  • Question about I/O expander connection
    #52 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   RFC
    • CLOSED
    • 1
    updated Apr 27, 2020
  • Pulldowns missing on IOEXP_RCLK and IOEXP_RESET
    #51 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   major
    • CLOSED
    • 1
    updated Apr 27, 2020
  • Do we need voltage translation to Vadj_FMC for FMC JTAG and I2C?
    #50 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   RFC
    • CLOSED
    • 1
    updated Apr 20, 2020
  • Use CERN library components
    #49 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   minor
    • CLOSED
    • 2
    updated Jul 19, 2020
  • CDCM61004 VCCVCO connection
    #48 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   design RFC
    • CLOSED
    • 1
    updated Apr 27, 2020
  • IC8 VIN decoupling cap value
    #47 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   RFC
    • CLOSED
    • 1
    updated Apr 27, 2020
  • LDO Soft-start time is set to 1s, is such a long time intentional?
    #46 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   RFC
    • CLOSED
    • 1
    updated Apr 27, 2020
  • AFPGA_1V0: mixed-up LDO feedback dividers
    #45 · opened Apr 20, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   critical
    • CLOSED
    • 1
    updated Apr 27, 2020
  • Perform test synthesis/P&R with the new pin assignment
    #41 · opened Apr 16, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   design
    • 0
    updated Apr 20, 2020
  • Documentation-related issues
    #40 · opened Apr 16, 2020 by Tomasz Wlostowski   Ready for PCB layout review.   minor
    • 0
    updated Jul 02, 2020
  • DDR3 swapped
    #38 · opened Apr 16, 2020 by Mattia Rizzi   Ready for PCB layout review.   critical
    • CLOSED
    • 4
    updated Apr 27, 2020
  • TPS74401RGWT bias
    #37 · opened Apr 15, 2020 by Mattia Rizzi   Ready for PCB layout review.   critical
    • CLOSED
    • 2
    updated Apr 27, 2020
  • P1V0 considerations
    #36 · opened Apr 15, 2020 by Mattia Rizzi   Ready for PCB layout review.   major
    • CLOSED
    • 1
    updated Apr 27, 2020
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