Issues · Projects / Simple VME FMC Carrier 7 - SVEC7 · Open Hardware Repository

FMC DP should be length matched

#90 · opened Jul 06, 2020 by Grzegorz Daniluk Ready for V1 prototype design minor
- CLOSED
- 4
updated Aug 20, 2020
update copyright in schematics and license to CERN OHL v2

#87 · opened Jul 06, 2020 by Grzegorz Daniluk Ready for V1 prototype minor
- CLOSED
- 1
updated Aug 13, 2020
Project name

#93 · opened Jul 08, 2020 by Evangelia Gousiou Ready for V1 prototype minor
- CLOSED
- 3
updated Jul 22, 2020
Use CERN library components

#49 · opened Apr 20, 2020 by Tomasz Wlostowski Ready for PCB layout review. minor
- CLOSED
- 2
updated Jul 19, 2020
Crosstalk

#97 · opened Jul 08, 2020 by Evangelia Gousiou Ready for V1 prototype minor
- CLOSED
- 4
updated Jul 19, 2020
Documentation-related issues

#40 · opened Apr 16, 2020 by Tomasz Wlostowski Ready for PCB layout review. minor
- 0
updated Jul 02, 2020
Pull up the DDR3_RESET_N instead of down?

#42 · opened Apr 20, 2020 by Tomasz Wlostowski minor
- CLOSED
- 2
updated Apr 27, 2020
AFPGA Flash/AFPGA configuration issues

#57 · opened Apr 20, 2020 by Tomasz Wlostowski Ready for PCB layout review. minor
- 3
updated Apr 27, 2020
Pin assignment of SFPGA-AFPGA link

#43 · opened Apr 20, 2020 by Tomasz Wlostowski minor
- CLOSED
- 3
updated Apr 27, 2020
VP_0 and VN_0

#35 · opened Apr 15, 2020 by Mattia Rizzi Ready for PCB layout review. minor
- CLOSED
- 1
updated Apr 27, 2020
Bypass caps in FT4232

#60 · opened Apr 20, 2020 by Tomasz Wlostowski Ready for PCB layout review. minor
- CLOSED
- 1
updated Apr 27, 2020