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Simple VME FMC Carrier 7 - SVEC7
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Simple VME FMC Carrier 7 - SVEC7
Issues
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12
Closed
85
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97
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Crosstalk
#97
· opened
Jul 08, 2020
by
Evangelia Gousiou
Ready for V1 prototype
minor
CLOSED
4
updated
Jul 19, 2020
Diff pairs impedance
#96
· opened
Jul 08, 2020
by
Evangelia Gousiou
Ready for V1 prototype
design
major
CLOSED
3
updated
Aug 13, 2020
Silkscreen
#95
· opened
Jul 08, 2020
by
Evangelia Gousiou
CLOSED
1
updated
Jul 12, 2020
PCB version
#94
· opened
Jul 08, 2020
by
Evangelia Gousiou
Ready for V1 prototype
design
major
CLOSED
3
updated
Jul 19, 2020
Project name
#93
· opened
Jul 08, 2020
by
Evangelia Gousiou
Ready for V1 prototype
minor
CLOSED
3
updated
Jul 22, 2020
FMC front panel mounting holes should be connected to chassis GND (not signal GND)
#92
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 19, 2020
FMC DP lines could be routed with soft corners for better SI
#91
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
FMC DP should be length matched
#90
· opened
Jul 06, 2020
by
Grzegorz Daniluk
Ready for V1 prototype
design
minor
CLOSED
4
updated
Aug 20, 2020
FMC LA should be length matched
#89
· opened
Jul 06, 2020
by
Grzegorz Daniluk
Ready for V1 prototype
design
major
CLOSED
3
updated
Jul 22, 2020
many traces have over-complicated routing, crossing layers multiple times
#88
· opened
Jul 06, 2020
by
Grzegorz Daniluk
2
updated
Jul 17, 2020
update copyright in schematics and license to CERN OHL v2
#87
· opened
Jul 06, 2020
by
Grzegorz Daniluk
Ready for V1 prototype
minor
CLOSED
1
updated
Aug 13, 2020
Don't we want cutouts below FMCs like on SPEC or DI/OT System Board?
#86
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
3
updated
Jul 21, 2020
Having Spartan-6 as SFPGA could again cause part obsolescence problem in a few years, why not Spartan-7 or Artix-7?
#85
· opened
Jul 06, 2020
by
Grzegorz Daniluk
2
updated
Jul 17, 2020
[L10] X:7217mil Y:6406mil - P1V0 polygon creates multiple acid traps
#84
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[L10] X:5647mil Y:4087mil - sumoptimal polygon shape around P3V3_FMC pad
#83
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[L10] X:5445mil Y:3854mil - possible acid trap
#82
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[L8] SFPGA-AFPGA link (SFPGA_TX_xx, SFPGA_RX_xx) crosses split power plane in L9
#81
· opened
Jul 06, 2020
by
Grzegorz Daniluk
1
updated
Jul 12, 2020
[L4] duplicate P5V_VME polygon on one more layer?
#80
· opened
Jul 06, 2020
by
Grzegorz Daniluk
0
updated
Jul 06, 2020
[L1] WR_MODDEV0..2, WR_TXDISABLE, WR_TXFAULT vias don't have to be so close together
#79
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Aug 13, 2020
[L1] J16 unnecessary, unused traces from S2, S3 pad
#78
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
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