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Simple VME FMC Carrier 7 - SVEC7
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Simple VME FMC Carrier 7 - SVEC7
Issues
Open
12
Closed
85
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97
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FPGA Bank Assignment
#12
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
0
updated
Feb 19, 2020
GTX Transcivers mapping
#11
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
1
updated
Feb 12, 2020
FMC Connectors
#10
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
0
updated
Feb 19, 2020
Power supply
3 of 3 tasks completed
#9
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
7
updated
Mar 23, 2020
Slow I/O
#8
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
3
updated
Feb 19, 2020
VME interface
3 of 4 tasks completed
#7
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
0
updated
Mar 01, 2020
Flash memory
#6
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
1
updated
Mar 01, 2020
Change the DDR memory to a DDR SO-DIMM module socket (no ECC)
#5
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
3
updated
Feb 19, 2020
Remove the discrete DDR chips (IC28, IC4)
#4
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
1
updated
Feb 10, 2020
Remove J1 and J16 (stand-alone power port)
#3
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
3
updated
Jul 02, 2020
Change the FPGA to XC7K160T-2FBG676
#1
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
1
updated
Feb 25, 2020
Crosstalk
#97
· opened
Jul 08, 2020
by
Evangelia Gousiou
Ready for V1 prototype
minor
CLOSED
4
updated
Jul 19, 2020
Diff pairs impedance
#96
· opened
Jul 08, 2020
by
Evangelia Gousiou
Ready for V1 prototype
design
major
CLOSED
3
updated
Aug 13, 2020
Silkscreen
#95
· opened
Jul 08, 2020
by
Evangelia Gousiou
CLOSED
1
updated
Jul 12, 2020
PCB version
#94
· opened
Jul 08, 2020
by
Evangelia Gousiou
Ready for V1 prototype
design
major
CLOSED
3
updated
Jul 19, 2020
Project name
#93
· opened
Jul 08, 2020
by
Evangelia Gousiou
Ready for V1 prototype
minor
CLOSED
3
updated
Jul 22, 2020
FMC front panel mounting holes should be connected to chassis GND (not signal GND)
#92
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 19, 2020
FMC DP lines could be routed with soft corners for better SI
#91
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
FMC DP should be length matched
#90
· opened
Jul 06, 2020
by
Grzegorz Daniluk
Ready for V1 prototype
design
minor
CLOSED
4
updated
Aug 20, 2020
FMC LA should be length matched
#89
· opened
Jul 06, 2020
by
Grzegorz Daniluk
Ready for V1 prototype
design
major
CLOSED
3
updated
Jul 22, 2020
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