Both CDCM61004 PLLs are configure for LVPECL outputs. Kintex-7 does not support 'native' LVPECL anymore - so we either need the clocks to be AC-coupled (+ level translated) or change to LVDS.

see: https://forums.xilinx.com/t5/Other-FPGA-Architecture/Does-kintex7-support-LVPECL-in-HR-bank/td-p/638212