Pull up the DDR3_RESET_N instead of down?
Reported by Dimitris.
Tom: IMHO default state (if the controller is off or the FPGA in not programmed) should be low so that the memory chip is in reset state.
Reported by Dimitris.
Tom: IMHO default state (if the controller is off or the FPGA in not programmed) should be low so that the memory chip is in reset state.