Simple VME FMC Carrier 7 - SVEC7 issueshttps://ohwr.org/project/svec7/issues2020-07-17T16:30:27Zhttps://ohwr.org/project/svec7/issues/88many traces have over-complicated routing, crossing layers multiple times2020-07-17T16:30:27ZGrzegorz Danilukmany traces have over-complicated routing, crossing layers multiple timesjust a few (not all!) examples:
- VMEPX_IRQ2_N goes multiple times from top to bottom again to top etc. while could be easily routed e.g. in L3.
- VME_D_DIR around pin d13 of VME P1 connector could be continuously routed in L5, but instead it goes to L3 and back.
- same for LCLK_N (X:7247mil Y:3588mil)https://ohwr.org/project/svec7/issues/85Having Spartan-6 as SFPGA could again cause part obsolescence problem in a fe...2020-07-17T16:33:33ZGrzegorz DanilukHaving Spartan-6 as SFPGA could again cause part obsolescence problem in a few years, why not Spartan-7 or Artix-7?https://ohwr.org/project/svec7/issues/81[L8] SFPGA-AFPGA link (SFPGA_TX_xx, SFPGA_RX_xx) crosses split power plane in L92020-07-12T11:35:57ZGrzegorz Daniluk[L8] SFPGA-AFPGA link (SFPGA_TX_xx, SFPGA_RX_xx) crosses split power plane in L9In general this link takes a very long path in L1, L3, L8. Maybe it could be
done in L5 if some part of FMC routing done there can be moved to L3?https://ohwr.org/project/svec7/issues/80[L4] duplicate P5V_VME polygon on one more layer?2020-07-06T06:46:30ZGrzegorz Daniluk[L4] duplicate P5V_VME polygon on one more layer?depending on the foreseen current from 5V VME connector pins (P5V_VME) maybe
it makes sense to duplicate P5V_VME polygon on one more layer?https://ohwr.org/project/svec7/issues/68No copper balancing2020-06-01T14:01:38ZPaweł KulikNo copper balancinghttps://ohwr.org/project/svec7/issues/63DiffPairsRouting rule2020-06-02T09:17:52ZPaweł KulikDiffPairsRouting ruleDiffPairsRouting rule uses impedance profile D100 which has manually specified width and gap values. Altium calculated diff impedance to be around 87-89, depending on layer. After changing Er from 4,8 to 4,2 it's still way below 100 Ohms.https://ohwr.org/project/svec7/issues/61Generate FPGA pinout2020-06-01T13:43:43ZMikolaj SowinskiGenerate FPGA pinoutAs soon as initial FPGA pinout is available (after pin swapping) please generate netlist for HDL verification, post here and notify @twlostow.Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/57AFPGA Flash/AFPGA configuration issues2020-04-27T16:54:25ZTomasz WlostowskiAFPGA Flash/AFPGA configuration issues- Quite misleading net names around IC50 (flash mux): AFPGA_CCLK is in fact coming from the SFPGA.
- Place a comment explaining that IC50 multiplexes between SFPGA (bootloader programming the AFPGA flash) and AFPGA (AFPGA startup from the AFPGA flash).
- IC51: why S25FL128 instead of M25P128 (used already in the project - it's 16 MBytes so should be sufficient in terms of size)?Ready for PCB layout review.https://ohwr.org/project/svec7/issues/41Perform test synthesis/P&R with the new pin assignment2020-04-20T16:10:26ZTomasz WlostowskiPerform test synthesis/P&R with the new pin assignmentDL: Have you tried this pin mapping and IO standards in ISE and Vivado?Ready for PCB layout review.Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec7/issues/40Documentation-related issues2020-07-02T14:37:32ZTomasz WlostowskiDocumentation-related issuesCommon thread for all coding style and documentation-related issues:
**Reported by Maciek Lipinski:**
- Some text is upside down, correct
- Update description (right bottom corner) on pages 17-21
- FMC slot 1, green letters indicating connectors are incorrect for
"I" and "J", should be "J" and "K" instead, the same problem with
connector names J2I and J2J, should be J2J and J2K (pdf page 5,
sheet 10)
- FMC slot 2, ideally, the naming of connectors would be consistent, i.e.
replace "J3D", "J3C", "J3B", and "J3A" with "J3H", "J3G", "J3B" and
"J3A". (pdf page 5, sheet 10)
**Reported by Dimitris Lampridis:**
General:
- On all pages, fix template info at bottom right. Project name, page description, EDA number,
people, dates, etc.
- The following pages use a different (and empty) template as well:
- DDR3 SODIMM
- AFPGA_FMC1_FMC2
- Slow_IO_Mux
- AFPGA_MISC
- AFPGA_1V0
- Fix the warnings reported by Altium after compilation (very few, nice!). If any is acceptable,
use a targeted no-ERC directive.
- Is there any particular reason why some nets have labels and others don't?
Top-level schematic:
- For the serial interface between the FPGAs, put a red "title" in the SFPGA block and change the
"user switches" red title in the AFPGA block to something meaningful. I also guess that the
rogue "user switches" red title at 4700,3700mil is from the SFPGA block.
- In the serial interface between FPGAs the _I and _O suffixes (and the whole RX/TX) on the net
labels are confusing. I would go for something explicit like bridge_s2a_dat, bridge_a2s_dat and
bridge_a2s_clk or something similar. I would use the same scheme in the HDL of both FPGAs as
well (with _i and _o in those).
- some diff signals have the differential directive on the top-level, others don't (they have it
inside some sheet of course). I'd prefer to stick with one approach, either all on the top
level, or all at the source (or all at the destination).
- I would use more harnesses, especially for things like the two identical sets of FMC signals
between AFPGA <-> FMC slots <-> GTP.
- I would rearrange the sheets and connections so that the Front Panel and FMC slots are the last
blocks on the right side of the page, with ports only on the left side of these sheet
symbols. It makes sense (to me at least): from VME on the left, through VME buffers, FPGAs, to
the front panel and FMC slots on the right.
- I would "hide" the FPGA power sheets under their respective FPGA top-level sheets. After all,
they are pins/sub-parts of the FPGA.
- Is there any particular reason why some nets have labels and others don't?
AFPGA:
- It would be nice to mention the FPGA banks used in each sheet symbol here, as well as the VCCIO
of each bank.
DDR3 SODIMM:
- Several DDR signals are active-low but their net labels lack the _N suffix.
- It is not immediately clear if SK1A is the top or bottom row of the DIMM socket.
- Also it is weird that a) we have two symbols, IC24 and SK1, with IC24 exactly on top of SK1 and
b) IC24 has no pins but all the signal names, while SK1 is the opposite.
- Missing differential directives on diff pairs
- Rename sheet to show that the bridge signals are also here.
- Missing no ERC on SODIMM CK1 pins.
AFPGA FMC1 FMC2:
- Any particular reason that the FMC pin order and slots are mixed? Does it help with layout?
Slow I/O Mux;
- This IMHO should be hierarchically "under" the AFPGA Misc sheet, not on the same level as the
other AFPGA sheets, because it does not contain any FPGA bank on itself and its ports would be
better grouped together with those of the AFPGA Misc sheet (e.g. the "FMC1 & FMC2" ports could
join the "FMC1" and "FMC2" port groups in the AFPGA Misc sheet symbol).
AFPGA Misc:
- Use capital letters for all ports
FPGA GTP:
- I would put the Kintex7 banks 115 and 116 hierarchicaly under the AFPGA sheet.
JTAG & SFPGA Flash:
- Rename sheet to remove the "SFPGA" from it, this now also has the AFPGA config.
- I would put the Kintex7 bank 0 hierarchicaly under the AFPGA sheet.
**Reported by Christos Gentsos:**
General:
- Page info has been left outdated, in some pages it's unpopulated
DDR3_SODIMM:
- The net DDR3_RESET should be renamed to DDR3_RESET_N, it's active low. Also assuming that it's
tied low to keep the RAM asleep until the FPGA is up and running?
- RAS/CAS/CS/WE signals are always low so there's no confusion but maybe their nets should get the _N,
too, for consistency
Slow_IO_MUX:
- The IOEXP_CLK_INH and IOEXP_SH/LD ports could be moved to the component above to slightly improve
readability
AFPGA_Misc:
- There are many nets that are labeled while only connected to hierarchical ports; the labels could
be removed for less clutter
JTAG chain + SFPGA flash
- It might be a good idea to move AFPGA above SFPGA, since it comes first in the JTAG chain.
VME_connectors
- Plenty of active-low signals are missing the _N but I don't know this isn't common notation in
this specific case, just noting
**Reported by Tom:**
- SFP port (113) names don't match with the FPGA GTX transceiver quad (115)
- Be consistent with IC names (ICxx or Uxx, we prefer ICxx).
- BOOT_CW port/BOOT_SW signal - keep the naming consistent.
Ready for PCB layout review.Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/39Licensing issues2020-04-20T16:11:02ZTomasz WlostowskiLicensing issuesReported by Maciek Lipinski:
Update license note: date (2014-2020) and possibly license (I guess we want v2.0, specify version).
Reported by Dimitris Lampridis:
- Fix copyright date and use OHLv2
https://ohwr.org/project/svec7/issues/7VME interface2020-03-01T18:12:27ZMikolaj SowinskiVME interfaceWe don’t have enough pins for a full VME interface in the AFPGA, therefore the SVEC7 will use a low pin
count inter-FPGA link to tunnel the VME traffic through the SFPGA. The pins are described in the table below:
![image](/uploads/d1fdd93e1745e9be7629d192034fe250/image.png)
![image](/uploads/16151f35396e5bb9c7f913b492da9b39/image.png)
All pins use the SSTL15 I/O standard, reusing the power supply/Vref of the DDR3 memory.
* [x] Please use the [supplied XDC file](https://www.ohwr.org/project/svec/blob/tom-svec7-test/hdl/syn/common/svec7/svec7.xdc#L491) for the pin assignment in the AFPGA.
* [x] On the SFPGA side, power an entire bank from 1.5V and supply the 0.75V Vref.
* [ ] All signals must be terminated on the far side (check Xilinx UG471).
* [x] The RSVD lines between the AFPGA and SFPGA can be dropped.
The 1.5V SFPGA bank can be also used for DIP switches (SWITCH0..1, NOGA0..5) and debug LEDs.Ready for schematic review (CTI internal)Michal GaskaMichal Gaska