Simple VME FMC Carrier 7 - SVEC7 issueshttps://ohwr.org/project/svec7/issues2020-07-19T10:35:15Zhttps://ohwr.org/project/svec7/issues/97Crosstalk2020-07-19T10:35:15ZEvangelia GousiouCrosstalkBottom Layer:
- FMC2_CLK1M2C_P travels over split lines of the L9 PWR polygons
- FMC1_DP3M2C_N travels over split lines of the L9 PWR polygons
L5/L6:
- Some diff pairs (ex FMC1_LA_P/N31) are crossing traces that are directly adjacent for long distances; increase distance to 5X?Ready for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/96Diff pairs impedance2020-08-13T08:34:13ZEvangelia GousiouDiff pairs impedanceThere could be some impedance issues; pictures below:
![Top](/uploads/1b0a82702db3e3b7438301b6a9491b84/Top.png)
![L3](/uploads/e5f1fc9f82e5f68ab9f745d6b502d34c/L3.png)
![L5](/uploads/3b70eda323c2fadd626c2b0e3c2dc978/L5.png)
![L6](/uploads/4dad10c9431c2501fb807b97b0c54234/L6.png)
![L8](/uploads/860910d7fac23d94f6308f067dde1f0e/L8.png)
![Bottom](/uploads/0b2620b21d1392864d14cedabea31010/Bottom.png)Ready for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/95Silkscreen2020-07-12T11:59:18ZEvangelia GousiouSilkscreenTop Silkscreen:
- Move P1V8 closer to B2
- TP are not actual Test Points, could be renamed?
- It is not clear what "FPGA MOSI" and "AFPGA CSO" refer to
- SW1: addition of some description for more user-friendliness
Bottom Silkscreen:
- Some components seem upside down:
C359, C352, C353, C357
R187, IC8, C43, C68, R150, LD19
C251, C252
C244, C247, C248, C142
C380, C378
C202, R97
C333
R137, R107https://ohwr.org/project/svec7/issues/94PCB version2020-07-19T10:34:58ZEvangelia GousiouPCB versionOn the pcbrev pins it seems like v2; the silkscreen says v1; the edms number mentions v3Ready for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/93Project name2020-07-22T13:47:32ZEvangelia GousiouProject nameThe Altium project name is SVEC not SVEC7 or EDA-xxxx
The pcb name is EDA-02530-V3-0_pcb which is exactly as the -old- SVECReady for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/92FMC front panel mounting holes should be connected to chassis GND (not signal...2020-07-19T11:53:01ZGrzegorz DanilukFMC front panel mounting holes should be connected to chassis GND (not signal GND)See Rule 3.19 and 3.21 of FMC specificationhttps://ohwr.org/project/svec7/issues/91FMC DP lines could be routed with soft corners for better SI2020-07-12T15:35:58ZGrzegorz DanilukFMC DP lines could be routed with soft corners for better SIhttps://ohwr.org/project/svec7/issues/90FMC DP should be length matched2020-08-20T09:00:52ZGrzegorz DanilukFMC DP should be length matchedcurrently for example: FMC1_DP3C2M is 2817mil vs FMC1_DP0C2M is 1805milReady for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/89FMC LA should be length matched2020-07-22T14:47:40ZGrzegorz DanilukFMC LA should be length matchedcurrently for example: FMC1_LA_33 is 3849mil vs FMC1_LA0 is 2568milReady for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/88many traces have over-complicated routing, crossing layers multiple times2020-07-17T16:30:27ZGrzegorz Danilukmany traces have over-complicated routing, crossing layers multiple timesjust a few (not all!) examples:
- VMEPX_IRQ2_N goes multiple times from top to bottom again to top etc. while could be easily routed e.g. in L3.
- VME_D_DIR around pin d13 of VME P1 connector could be continuously routed in L5, but instead it goes to L3 and back.
- same for LCLK_N (X:7247mil Y:3588mil)https://ohwr.org/project/svec7/issues/87update copyright in schematics and license to CERN OHL v22020-08-13T08:58:14ZGrzegorz Danilukupdate copyright in schematics and license to CERN OHL v2Ready for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/86Don't we want cutouts below FMCs like on SPEC or DI/OT System Board?2020-07-21T15:43:31ZGrzegorz DanilukDon't we want cutouts below FMCs like on SPEC or DI/OT System Board?https://ohwr.org/project/svec7/issues/85Having Spartan-6 as SFPGA could again cause part obsolescence problem in a fe...2020-07-17T16:33:33ZGrzegorz DanilukHaving Spartan-6 as SFPGA could again cause part obsolescence problem in a few years, why not Spartan-7 or Artix-7?https://ohwr.org/project/svec7/issues/84[L10] X:7217mil Y:6406mil - P1V0 polygon creates multiple acid traps2020-07-12T10:51:10ZGrzegorz Daniluk[L10] X:7217mil Y:6406mil - P1V0 polygon creates multiple acid trapshttps://ohwr.org/project/svec7/issues/83[L10] X:5647mil Y:4087mil - sumoptimal polygon shape around P3V3_FMC pad2020-07-12T10:33:29ZGrzegorz Daniluk[L10] X:5647mil Y:4087mil - sumoptimal polygon shape around P3V3_FMC padhttps://ohwr.org/project/svec7/issues/82[L10] X:5445mil Y:3854mil - possible acid trap2020-07-12T10:30:18ZGrzegorz Daniluk[L10] X:5445mil Y:3854mil - possible acid traphttps://ohwr.org/project/svec7/issues/81[L8] SFPGA-AFPGA link (SFPGA_TX_xx, SFPGA_RX_xx) crosses split power plane in L92020-07-12T11:35:57ZGrzegorz Daniluk[L8] SFPGA-AFPGA link (SFPGA_TX_xx, SFPGA_RX_xx) crosses split power plane in L9In general this link takes a very long path in L1, L3, L8. Maybe it could be
done in L5 if some part of FMC routing done there can be moved to L3?https://ohwr.org/project/svec7/issues/80[L4] duplicate P5V_VME polygon on one more layer?2020-07-06T06:46:30ZGrzegorz Daniluk[L4] duplicate P5V_VME polygon on one more layer?depending on the foreseen current from 5V VME connector pins (P5V_VME) maybe
it makes sense to duplicate P5V_VME polygon on one more layer?https://ohwr.org/project/svec7/issues/79[L1] WR_MODDEV0..2, WR_TXDISABLE, WR_TXFAULT vias don't have to be so close t...2020-08-13T08:36:29ZGrzegorz Daniluk[L1] WR_MODDEV0..2, WR_TXDISABLE, WR_TXFAULT vias don't have to be so close togetherWR_MODDEV0..2, WR_TXDISABLE, WR_TXFAULT vias next to SFP don't have to be so
close together, anyway in L3 and L5 where there are connected to tracks there
is plenty of space to spread them and place vias next to the pads in L1.https://ohwr.org/project/svec7/issues/78[L1] J16 unnecessary, unused traces from S2, S3 pad2020-07-12T10:07:43ZGrzegorz Daniluk[L1] J16 unnecessary, unused traces from S2, S3 pad