Simple VME FMC Carrier 7 - SVEC7 issueshttps://ohwr.org/project/svec7/issues2020-03-20T15:50:45Zhttps://ohwr.org/project/svec7/issues/23Missing capacitors - SFPGA2020-03-20T15:50:45ZFilip ŚwitakowskiMissing capacitors - SFPGAMissing capacitors for P1V5 bankMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/89FMC LA should be length matched2020-07-22T14:47:40ZGrzegorz DanilukFMC LA should be length matchedcurrently for example: FMC1_LA_33 is 3849mil vs FMC1_LA0 is 2568milReady for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/76[TSilk] "PCIe data" and "PCIe clock & SUPPLY" refers to what exactly? The con...2020-07-12T10:34:07ZGrzegorz Daniluk[TSilk] "PCIe data" and "PCIe clock & SUPPLY" refers to what exactly? The connector above provides only power.https://ohwr.org/project/svec7/issues/77[TSilk] Add text "HPC" and "LPC" to indicate the type of FMC slot.2020-07-12T10:34:53ZGrzegorz Daniluk[TSilk] Add text "HPC" and "LPC" to indicate the type of FMC slot.https://ohwr.org/project/svec7/issues/84[L10] X:7217mil Y:6406mil - P1V0 polygon creates multiple acid traps2020-07-12T10:51:10ZGrzegorz Daniluk[L10] X:7217mil Y:6406mil - P1V0 polygon creates multiple acid trapshttps://ohwr.org/project/svec7/issues/6Flash memory2020-03-01T18:25:46ZMikolaj SowinskiFlash memoryAdd a separate flash for bitstream storage for the AFPGA connected to Xilinx’s boot SPI interface. This flash
must be also connected to the SFPGA, so that the bootloader can access it.Ready for schematic review (CTI internal)Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/3Remove J1 and J16 (stand-alone power port)2020-07-02T14:38:43ZMikolaj SowinskiRemove J1 and J16 (stand-alone power port)Ready for schematic review (CTI internal)Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/4Remove the discrete DDR chips (IC28, IC4)2020-02-10T08:32:33ZMikolaj SowinskiRemove the discrete DDR chips (IC28, IC4)Ready for schematic review (CTI internal)Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/29Schematics conventions2020-03-19T10:00:11ZFilip ŚwitakowskiSchematics conventionsPlease change following schematic sheet sizes from A4 to A3, and add OHL license: Slow_IO_MUX, AFPGA_MISC, AFPGA_1V0.Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/94PCB version2020-07-19T10:34:58ZEvangelia GousiouPCB versionOn the pcbrev pins it seems like v2; the silkscreen says v1; the edms number mentions v3Ready for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/34sfpga: read dtack2020-07-12T10:58:12ZTristan Gingoldsfpga: read dtackIt would be nice if the sfpga could read the current dtack value from the VME bus (even when it doesn't drive it).
The purpose is to be able to spy or analyze the VME bus.
Bonus point if retry and berr could also be read.Ready for PCB layout review.Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/24Missing PU/PD resistors2020-03-19T10:21:08ZFilip ŚwitakowskiMissing PU/PD resistorsPlease add PU and PD 1k resistors to PUDC B25 pin of IC4. Add mounting variant with PU mounted.Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/82[L10] X:5445mil Y:3854mil - possible acid trap2020-07-12T10:30:18ZGrzegorz Daniluk[L10] X:5445mil Y:3854mil - possible acid traphttps://ohwr.org/project/svec7/issues/83[L10] X:5647mil Y:4087mil - sumoptimal polygon shape around P3V3_FMC pad2020-07-12T10:33:29ZGrzegorz Daniluk[L10] X:5647mil Y:4087mil - sumoptimal polygon shape around P3V3_FMC padhttps://ohwr.org/project/svec7/issues/86Don't we want cutouts below FMCs like on SPEC or DI/OT System Board?2020-07-21T15:43:31ZGrzegorz DanilukDon't we want cutouts below FMCs like on SPEC or DI/OT System Board?https://ohwr.org/project/svec7/issues/87update copyright in schematics and license to CERN OHL v22020-08-13T08:58:14ZGrzegorz Danilukupdate copyright in schematics and license to CERN OHL v2Ready for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/90FMC DP should be length matched2020-08-20T09:00:52ZGrzegorz DanilukFMC DP should be length matchedcurrently for example: FMC1_DP3C2M is 2817mil vs FMC1_DP0C2M is 1805milReady for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/91FMC DP lines could be routed with soft corners for better SI2020-07-12T15:35:58ZGrzegorz DanilukFMC DP lines could be routed with soft corners for better SIhttps://ohwr.org/project/svec7/issues/28Change THT caps to SMD2020-03-20T15:51:19ZFilip ŚwitakowskiChange THT caps to SMD@twlostow can we change THT capacitors to SMD?
C224, C225, C182, C60, C179, C170, C44, C221, C175, C435https://ohwr.org/project/svec7/issues/30Memory symbols IC24A and IC24B are swapped2020-03-19T09:58:18ZFilip ŚwitakowskiMemory symbols IC24A and IC24B are swappedMichal GaskaMichal Gaska