Simple VME FMC Carrier 7 - SVEC7 issueshttps://ohwr.org/project/svec7/issues2020-03-20T15:14:32Zhttps://ohwr.org/project/svec7/issues/19Add TP to Vadj_FMC2020-03-20T15:14:32ZFilip ŚwitakowskiAdd TP to Vadj_FMCAdd Test pointMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/22Unconnected Signals2020-03-20T15:44:55ZFilip ŚwitakowskiUnconnected Signals1. FMC1_VREFAM2C
2. FMC2_VREFAM2C
3. P2_DATA - group of signalsMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/7VME interface2020-03-01T18:12:27ZMikolaj SowinskiVME interfaceWe don’t have enough pins for a full VME interface in the AFPGA, therefore the SVEC7 will use a low pin
count inter-FPGA link to tunnel the VME traffic through the SFPGA. The pins are described in the table below:
![image](/uploads/d1fdd93e1745e9be7629d192034fe250/image.png)
![image](/uploads/16151f35396e5bb9c7f913b492da9b39/image.png)
All pins use the SSTL15 I/O standard, reusing the power supply/Vref of the DDR3 memory.
* [x] Please use the [supplied XDC file](https://www.ohwr.org/project/svec/blob/tom-svec7-test/hdl/syn/common/svec7/svec7.xdc#L491) for the pin assignment in the AFPGA.
* [x] On the SFPGA side, power an entire bank from 1.5V and supply the 0.75V Vref.
* [ ] All signals must be terminated on the far side (check Xilinx UG471).
* [x] The RSVD lines between the AFPGA and SFPGA can be dropped.
The 1.5V SFPGA bank can be also used for DIP switches (SWITCH0..1, NOGA0..5) and debug LEDs.Ready for schematic review (CTI internal)Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/40Documentation-related issues2020-07-02T14:37:32ZTomasz WlostowskiDocumentation-related issuesCommon thread for all coding style and documentation-related issues:
**Reported by Maciek Lipinski:**
- Some text is upside down, correct
- Update description (right bottom corner) on pages 17-21
- FMC slot 1, green letters indicating connectors are incorrect for
"I" and "J", should be "J" and "K" instead, the same problem with
connector names J2I and J2J, should be J2J and J2K (pdf page 5,
sheet 10)
- FMC slot 2, ideally, the naming of connectors would be consistent, i.e.
replace "J3D", "J3C", "J3B", and "J3A" with "J3H", "J3G", "J3B" and
"J3A". (pdf page 5, sheet 10)
**Reported by Dimitris Lampridis:**
General:
- On all pages, fix template info at bottom right. Project name, page description, EDA number,
people, dates, etc.
- The following pages use a different (and empty) template as well:
- DDR3 SODIMM
- AFPGA_FMC1_FMC2
- Slow_IO_Mux
- AFPGA_MISC
- AFPGA_1V0
- Fix the warnings reported by Altium after compilation (very few, nice!). If any is acceptable,
use a targeted no-ERC directive.
- Is there any particular reason why some nets have labels and others don't?
Top-level schematic:
- For the serial interface between the FPGAs, put a red "title" in the SFPGA block and change the
"user switches" red title in the AFPGA block to something meaningful. I also guess that the
rogue "user switches" red title at 4700,3700mil is from the SFPGA block.
- In the serial interface between FPGAs the _I and _O suffixes (and the whole RX/TX) on the net
labels are confusing. I would go for something explicit like bridge_s2a_dat, bridge_a2s_dat and
bridge_a2s_clk or something similar. I would use the same scheme in the HDL of both FPGAs as
well (with _i and _o in those).
- some diff signals have the differential directive on the top-level, others don't (they have it
inside some sheet of course). I'd prefer to stick with one approach, either all on the top
level, or all at the source (or all at the destination).
- I would use more harnesses, especially for things like the two identical sets of FMC signals
between AFPGA <-> FMC slots <-> GTP.
- I would rearrange the sheets and connections so that the Front Panel and FMC slots are the last
blocks on the right side of the page, with ports only on the left side of these sheet
symbols. It makes sense (to me at least): from VME on the left, through VME buffers, FPGAs, to
the front panel and FMC slots on the right.
- I would "hide" the FPGA power sheets under their respective FPGA top-level sheets. After all,
they are pins/sub-parts of the FPGA.
- Is there any particular reason why some nets have labels and others don't?
AFPGA:
- It would be nice to mention the FPGA banks used in each sheet symbol here, as well as the VCCIO
of each bank.
DDR3 SODIMM:
- Several DDR signals are active-low but their net labels lack the _N suffix.
- It is not immediately clear if SK1A is the top or bottom row of the DIMM socket.
- Also it is weird that a) we have two symbols, IC24 and SK1, with IC24 exactly on top of SK1 and
b) IC24 has no pins but all the signal names, while SK1 is the opposite.
- Missing differential directives on diff pairs
- Rename sheet to show that the bridge signals are also here.
- Missing no ERC on SODIMM CK1 pins.
AFPGA FMC1 FMC2:
- Any particular reason that the FMC pin order and slots are mixed? Does it help with layout?
Slow I/O Mux;
- This IMHO should be hierarchically "under" the AFPGA Misc sheet, not on the same level as the
other AFPGA sheets, because it does not contain any FPGA bank on itself and its ports would be
better grouped together with those of the AFPGA Misc sheet (e.g. the "FMC1 & FMC2" ports could
join the "FMC1" and "FMC2" port groups in the AFPGA Misc sheet symbol).
AFPGA Misc:
- Use capital letters for all ports
FPGA GTP:
- I would put the Kintex7 banks 115 and 116 hierarchicaly under the AFPGA sheet.
JTAG & SFPGA Flash:
- Rename sheet to remove the "SFPGA" from it, this now also has the AFPGA config.
- I would put the Kintex7 bank 0 hierarchicaly under the AFPGA sheet.
**Reported by Christos Gentsos:**
General:
- Page info has been left outdated, in some pages it's unpopulated
DDR3_SODIMM:
- The net DDR3_RESET should be renamed to DDR3_RESET_N, it's active low. Also assuming that it's
tied low to keep the RAM asleep until the FPGA is up and running?
- RAS/CAS/CS/WE signals are always low so there's no confusion but maybe their nets should get the _N,
too, for consistency
Slow_IO_MUX:
- The IOEXP_CLK_INH and IOEXP_SH/LD ports could be moved to the component above to slightly improve
readability
AFPGA_Misc:
- There are many nets that are labeled while only connected to hierarchical ports; the labels could
be removed for less clutter
JTAG chain + SFPGA flash
- It might be a good idea to move AFPGA above SFPGA, since it comes first in the JTAG chain.
VME_connectors
- Plenty of active-low signals are missing the _N but I don't know this isn't common notation in
this specific case, just noting
**Reported by Tom:**
- SFP port (113) names don't match with the FPGA GTX transceiver quad (115)
- Be consistent with IC names (ICxx or Uxx, we prefer ICxx).
- BOOT_CW port/BOOT_SW signal - keep the naming consistent.
Ready for PCB layout review.Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/8Slow I/O2020-02-19T10:35:28ZMikolaj SowinskiSlow I/OIn order to further reduce the number of required pins in the AFPGA, some of the slow I/Os of the SVEC will be
moved to an I/O expander. Use the 74LV595/74LV166 shift registers as the I/O expanders an connect them to
the the [ioexp_ pins](https://www.ohwr.org/project/svec/blob/tom-svec7-test/hdl/syn/common/svec7/svec7.xdc#L641) of the AFPGA.
![image](/uploads/5b308c2b5cba595b8786102370ea0977/image.png)
![image](/uploads/6696346ae4df28df4a012f4264507bc5/image.png)Ready for schematic review (CTI internal)Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/11GTX Transcivers mapping2020-02-12T08:19:37ZMikolaj SowinskiGTX Transcivers mapping![image](/uploads/cf520e6f9eed059950bbfa15bfbab33e/image.png)
Notes:
- GTX bank swapping is permitted (confirm this with CERN during layout to check if P&R is happy)
- GTX intra-bank clock and channel swapping is permitted (confirm, please)Ready for schematic review (CTI internal)Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/20MGT power2020-03-20T15:42:50ZFilip ŚwitakowskiMGT powerIt pertain to all MGT loads.
DS says that: "The power supply regulator for this voltage should not be shared with non-MGT loads."Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/2Use FT2232 instead of CP21032020-02-25T08:53:45ZMikolaj SowinskiUse FT2232 instead of CP2103If FT2232 is used instead of CP2103 it can be used both as USB-Serial and JTAG for programming FPGA (OpenOCD supports it).
[Kasli](https://github.com/sinara-hw/Kasli) can be used as a reference design.Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/18Kintex Vadj2020-03-16T13:32:23ZFilip ŚwitakowskiKintex VadjVadj isn't connected to Vadj_FMCMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/35VP_0 and VN_02020-04-27T15:20:26ZMattia RizziVP_0 and VN_0Connect to GND according to the XADC User Guide pg 14:
http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
"This pin should be connected to GND if not used."Ready for PCB layout review.https://ohwr.org/project/svec7/issues/32Fuse - P3V3_FMC2020-03-19T09:57:05ZFilip ŚwitakowskiFuse - P3V3_FMCPlease remove F3 and F4, and add one to P3V3_FMC and maybe one to P12V_FMCMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/43Pin assignment of SFPGA-AFPGA link2020-04-27T15:51:11ZTomasz WlostowskiPin assignment of SFPGA-AFPGA linkReported by Dimitris:
Is it not possible to place the SFPGA_RX<*> in adjacent pins? Think of the placement inside the
FPGA, especially if the signals are on different banks. Bank 33 seems to have enough free pins
to have all the SFPGA_RX, TX and clock, all close to each other.Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec7/issues/9Power supply2020-03-23T10:04:16ZMikolaj SowinskiPower supply* [x] Put a load switch on +3.3V and +12V on both FMC slots allowing the FPGA to switch on/off the payload FMC
voltages. Each voltage has to be controlled separately (2 enable lines).
* [x] Allow adjusting IC9 regulator output voltages and on/off state, the voltage has to be controlled from the
AFPGA. The user should be able to choose the Vadj from the set of predefined values: +1.8V, +2.5V, +3.3V. By
default Vadj should be OFF. Both slots share the same Vadj.
* [x] Adapt supply voltages for the Kintex-7 FPGA (1.0 Vcore/1.2V VGtx)Ready for schematic review (CTI internal)Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/59VAdj PSU should be controlled by the AFPGA2020-04-27T14:46:12ZTomasz WlostowskiVAdj PSU should be controlled by the AFPGAConnect PS_FMC_2V5, PS_FMC_3V3 and PS_FMC_EN_VADJ to the AFPGA. The SFPGA doesn't have the access to the FMC EEPROMs so it can't know anyway how to configure the Vadj voltage.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/47IC8 VIN decoupling cap value2020-04-27T16:11:57ZTomasz WlostowskiIC8 VIN decoupling cap valueFrom Christos.
About the decoupling cap at the VIN pin of IC8, the datasheet mentions a value between 1uF and
4.7uF. I don't think that 22uF would actually be a problem but I thought it was worth a mention.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/38DDR3 swapped2020-04-27T14:55:06ZMattia RizziDDR3 swappedFrom the schematics, DDR3 should be swapped, so that IC24A match SK1AReady for PCB layout review.https://ohwr.org/project/svec7/issues/45AFPGA_1V0: mixed-up LDO feedback dividers2020-04-27T15:01:28ZTomasz WlostowskiAFPGA_1V0: mixed-up LDO feedback dividers**From Christos:**
There's been a mixup with the LDO resistor dividers: the 1.0V one actually sets it for 1.2V, and
the 1.2V LDO is set for 1.05V, according to the datasheetReady for PCB layout review.https://ohwr.org/project/svec7/issues/53IC4C: swapped Flash_MISO and Flash_MOSI lines.2020-04-27T16:02:30ZTomasz WlostowskiIC4C: swapped Flash_MISO and Flash_MOSI lines.Also make sure MISO/MOSI labels on the nets are consistent with the names of the pins...Ready for PCB layout review.https://ohwr.org/project/svec7/issues/39Licensing issues2020-04-20T16:11:02ZTomasz WlostowskiLicensing issuesReported by Maciek Lipinski:
Update license note: date (2014-2020) and possibly license (I guess we want v2.0, specify version).
Reported by Dimitris Lampridis:
- Fix copyright date and use OHLv2
https://ohwr.org/project/svec7/issues/48CDCM61004 VCCVCO connection2020-04-27T16:06:04ZTomasz WlostowskiCDCM61004 VCCVCO connectionFrom Christos.
According to the datasheet, VCCVCO is to be tied to VCCPLL1 and VCCPLL2, and VCCIN to VCCOUT. Here
(and in existing designs so it's definitely not grave, perhaps sub-optimal?), VCCVCO goes with
VCCIN and VCCOUT.Ready for PCB layout review.