Simple VME FMC Carrier 7 - SVEC7 issueshttps://ohwr.org/project/svec7/issues2020-07-12T10:34:53Zhttps://ohwr.org/project/svec7/issues/77[TSilk] Add text "HPC" and "LPC" to indicate the type of FMC slot.2020-07-12T10:34:53ZGrzegorz Daniluk[TSilk] Add text "HPC" and "LPC" to indicate the type of FMC slot.https://ohwr.org/project/svec7/issues/76[TSilk] "PCIe data" and "PCIe clock & SUPPLY" refers to what exactly? The con...2020-07-12T10:34:07ZGrzegorz Daniluk[TSilk] "PCIe data" and "PCIe clock & SUPPLY" refers to what exactly? The connector above provides only power.https://ohwr.org/project/svec7/issues/75IC8 doesn't have thermal relief vias2020-06-02T08:42:32ZPaweł KulikIC8 doesn't have thermal relief viasIt should have them per TI's datasheethttps://ohwr.org/project/svec7/issues/74DDR reference plane continuity2020-06-04T16:20:51ZPaweł KulikDDR reference plane continuityWhen changing layers bottom to and from top reference plane is changed from GND to and from P1V5. In most cases closest P1V5 via is far away, cap for P1V5 even further.https://ohwr.org/project/svec7/issues/73Reference plane continuity for differential pairs problems2020-06-04T19:06:15ZPaweł KulikReference plane continuity for differential pairs problemsGenerally there are problems with reference planes when changing layer from bottom or L8 to higher layers.
* [x] ![reference1](/uploads/f1f8487c837c699aa99f71c3abe75979/reference1.PNG)
* [x] On L8 many pairs cross different L9 planes
![reference2](/uploads/79da4521a78f662ca6880dc4e3dc4f7e/reference2.JPG)
* [x] ![reference3](/uploads/8d41687a36988ecbb7df092d7d554ab6/reference3.JPG)
* [x] Differential lines on bottom cross different L9 planes
![reference4](/uploads/7c97244e85e5951e176acb1a45ff15f3/reference4.JPG)
* [x] ![reference5](/uploads/45846777d0a8fb15aef017695f4ed3d2/reference5.JPG)
* [x] Reference plane changes from P1V2 to P1V5/GND, one GND via is not enough for this SFP signal
![reference6sfp](/uploads/a4d63e21f6a4f2e0f62ab0a4b5f8012f/reference6sfp.JPG)
* [x] Reference plane changes from power to GND, there should be a capacitor or two around here
![reference7gt](/uploads/c556a9541e87b3ee6336ed25cbd5f243/reference7gt.JPG)
* [x] Same here
![referencech1](/uploads/f3cc4a223a15102988b775fb42fff817/referencech1.JPG)
* [x] And here
![referencech2](/uploads/65407f6913ed82701bdd7e021d3d8810/referencech2.PNG)
* [x] There should be more vias here to avoid interference
![przelotki](/uploads/f458589015b8fe8310b72d1da3aaaaad/przelotki.JPG)https://ohwr.org/project/svec7/issues/728 silkscreen strings are outside of the board2020-06-04T15:55:40ZPaweł Kulik8 silkscreen strings are outside of the boardhttps://ohwr.org/project/svec7/issues/71Change name of the board in silkscreen2020-06-02T08:50:17ZPaweł KulikChange name of the board in silkscreenhttps://ohwr.org/project/svec7/issues/70OHWR license on PCB should be newer2020-06-04T16:08:51ZPaweł KulikOHWR license on PCB should be newerhttps://ohwr.org/project/svec7/issues/69No heatsink on K72020-07-22T14:48:44ZPaweł KulikNo heatsink on K7Did someone check if it's possible to mount clip-on heatsink? Should there be mounting holes for heatsink?Ready for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/68No copper balancing2020-06-01T14:01:38ZPaweł KulikNo copper balancinghttps://ohwr.org/project/svec7/issues/67Stackup table2020-06-04T19:06:33ZPaweł KulikStackup tableStackup table on PCB:
* [x] 50 Ohm controlled impedance should be changed to 40 Ohm
* [ ] Line width/gap is imo wrong (see #63)https://ohwr.org/project/svec7/issues/66Vias under SMD pads should be unmasked2020-06-02T09:02:09ZPaweł KulikVias under SMD pads should be unmasked(thermal relief vias)https://ohwr.org/project/svec7/issues/65Matched length between DDR address and data2020-06-04T15:57:52ZPaweł KulikMatched length between DDR address and dataShouldn't there be a rule to match length between DDR address and data?https://ohwr.org/project/svec7/issues/64No matched net length within differential pair2020-06-04T15:56:44ZPaweł KulikNo matched net length within differential pairShouldn't there be a global rule for matched length within differential pairs?https://ohwr.org/project/svec7/issues/63DiffPairsRouting rule2020-06-02T09:17:52ZPaweł KulikDiffPairsRouting ruleDiffPairsRouting rule uses impedance profile D100 which has manually specified width and gap values. Altium calculated diff impedance to be around 87-89, depending on layer. After changing Er from 4,8 to 4,2 it's still way below 100 Ohms.https://ohwr.org/project/svec7/issues/62DRC check2020-06-04T16:41:59ZPaweł KulikDRC checkBoard outline clearance, hole size, hole to hole clearance, minimum solder mask sliver, silk to solder mask clearance, matched lengths rules were disabled during DRC check initially. After enabling them there were 41 silk to solder mask violations and 1 matched net length violation.https://ohwr.org/project/svec7/issues/61Generate FPGA pinout2020-06-01T13:43:43ZMikolaj SowinskiGenerate FPGA pinoutAs soon as initial FPGA pinout is available (after pin swapping) please generate netlist for HDL verification, post here and notify @twlostow.Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/60Bypass caps in FT42322020-04-27T14:26:36ZTomasz WlostowskiBypass caps in FT4232FT4232: should we have some extra bypass capacitors on VCORE pins?Ready for PCB layout review.https://ohwr.org/project/svec7/issues/59VAdj PSU should be controlled by the AFPGA2020-04-27T14:46:12ZTomasz WlostowskiVAdj PSU should be controlled by the AFPGAConnect PS_FMC_2V5, PS_FMC_3V3 and PS_FMC_EN_VADJ to the AFPGA. The SFPGA doesn't have the access to the FMC EEPROMs so it can't know anyway how to configure the Vadj voltage.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/58AFPGA can't be programmed from SFPGA on-the-fly2020-07-22T14:49:23ZTomasz WlostowskiAFPGA can't be programmed from SFPGA on-the-flyWe can't have direct SFPGA->AFPGA boot (SFPGA uploading the bitstream to AFPGA directly from VME) anymore as FPGA_CCLK/Flash_MISO/Flash_MOSI/Flash_CS lines can't be driven by the SFPGA anymore.
They are connected each to connected to the B1/B2 pins of the mux, which doesn't allow the B1/B2 pins to be shorted together.
Furthermore, the MODE pins of the AFPGA are driven by jumpers. The SFPGA should be able to override the boot mode and put the AFPGA in Passive Serial configuration mode in order to boot on the fly from VME.Ready for V1 prototypeMichal GaskaMichal Gaska