Simple VME FMC Carrier 7 - SVEC7 issueshttps://ohwr.org/project/svec7/issues2020-07-12T10:58:12Zhttps://ohwr.org/project/svec7/issues/34sfpga: read dtack2020-07-12T10:58:12ZTristan Gingoldsfpga: read dtackIt would be nice if the sfpga could read the current dtack value from the VME bus (even when it doesn't drive it).
The purpose is to be able to spy or analyze the VME bus.
Bonus point if retry and berr could also be read.Ready for PCB layout review.Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/33Add serial EEPROM that are preprogrammed with MAC address2020-04-27T15:06:59ZErik van der BijAdd serial EEPROM that are preprogrammed with MAC addressConsider adding the same Serial EEPROMs as those used on the [SPEC7](https://www.ohwr.org/project/spec7/wikis) to have always a MAC address on the card:
- 2x 2K (128 x 8-bit) I2C Serial EEPROM (24AA025E48) which provides EUI-48
- one for APU MAC address
- one for WR MAC addressReady for PCB layout review.Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/60Bypass caps in FT42322020-04-27T14:26:36ZTomasz WlostowskiBypass caps in FT4232FT4232: should we have some extra bypass capacitors on VCORE pins?Ready for PCB layout review.https://ohwr.org/project/svec7/issues/59VAdj PSU should be controlled by the AFPGA2020-04-27T14:46:12ZTomasz WlostowskiVAdj PSU should be controlled by the AFPGAConnect PS_FMC_2V5, PS_FMC_3V3 and PS_FMC_EN_VADJ to the AFPGA. The SFPGA doesn't have the access to the FMC EEPROMs so it can't know anyway how to configure the Vadj voltage.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/57AFPGA Flash/AFPGA configuration issues2020-04-27T16:54:25ZTomasz WlostowskiAFPGA Flash/AFPGA configuration issues- Quite misleading net names around IC50 (flash mux): AFPGA_CCLK is in fact coming from the SFPGA.
- Place a comment explaining that IC50 multiplexes between SFPGA (bootloader programming the AFPGA flash) and AFPGA (AFPGA startup from the AFPGA flash).
- IC51: why S25FL128 instead of M25P128 (used already in the project - it's 16 MBytes so should be sufficient in terms of size)?Ready for PCB layout review.https://ohwr.org/project/svec7/issues/56Clocking: consider removing IC20 and SFP_CLK?2020-04-27T15:43:15ZTomasz WlostowskiClocking: consider removing IC20 and SFP_CLK?Many years ago (around 2010) we had a plan to develop a special copper SFP that would use the 125 MHz PLL clock for fully synchronous operation... We've never done that, so it's safe to say after 10 years this circuit will not be used.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/55Clocking: remove PLLFMC1_CLK/PLLFMC2_CLK.2020-04-27T16:01:07ZTomasz WlostowskiClocking: remove PLLFMC1_CLK/PLLFMC2_CLK.After a quick discussion (thanks Erik!) we concluded it was added for historical compatibility with the VFC card and never used in practice. It's safe to remove it (including the UFL and P2 connections).
------------ old message ----------
CERNies, does anybody remember why these lines were added in the original SVEC design (asking because we can't have both LVPECL and LVDS outputs in the CDCM61004 and these lines have fixed LVPECL bias resistors)?
Ready for PCB layout review.https://ohwr.org/project/svec7/issues/54Clocking: Kintex-7 doesn't support LVPECL.2020-09-24T14:11:42ZTomasz WlostowskiClocking: Kintex-7 doesn't support LVPECL.Both CDCM61004 PLLs are configure for LVPECL outputs. Kintex-7 does not support 'native' LVPECL anymore - so we either need the clocks to be AC-coupled (+ level translated) or change to LVDS.
see: https://forums.xilinx.com/t5/Other-FPGA-Architecture/Does-kintex7-support-LVPECL-in-HR-bank/td-p/638212Ready for PCB layout review.https://ohwr.org/project/svec7/issues/53IC4C: swapped Flash_MISO and Flash_MOSI lines.2020-04-27T16:02:30ZTomasz WlostowskiIC4C: swapped Flash_MISO and Flash_MOSI lines.Also make sure MISO/MOSI labels on the nets are consistent with the names of the pins...Ready for PCB layout review.https://ohwr.org/project/svec7/issues/52Question about I/O expander connection2020-04-27T16:33:23ZTomasz WlostowskiQuestion about I/O expander connectionIs there a reason for connecting U1-1 (input shift register cascade input) with the serial output of the output shift register (IC41-9)?Ready for PCB layout review.Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/51Pulldowns missing on IOEXP_RCLK and IOEXP_RESET2020-04-27T16:48:25ZTomasz WlostowskiPulldowns missing on IOEXP_RCLK and IOEXP_RESETConsider adding strong pulldowns (say, 1k) on IOEXP_RCLK and IOEXP_RESET. The I/O expanders should drive default values (0) when the AFPGA is unprogrammed.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/50Do we need voltage translation to Vadj_FMC for FMC JTAG and I2C?2020-04-20T21:59:43ZTomasz WlostowskiDo we need voltage translation to Vadj_FMC for FMC JTAG and I2C?Reported by Christos.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/49Use CERN library components2020-07-19T10:40:55ZTomasz WlostowskiUse CERN library componentsReported by Christos:
- SN74LV166ANSR is not taken from the CERN Altium library.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/48CDCM61004 VCCVCO connection2020-04-27T16:06:04ZTomasz WlostowskiCDCM61004 VCCVCO connectionFrom Christos.
According to the datasheet, VCCVCO is to be tied to VCCPLL1 and VCCPLL2, and VCCIN to VCCOUT. Here
(and in existing designs so it's definitely not grave, perhaps sub-optimal?), VCCVCO goes with
VCCIN and VCCOUT.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/47IC8 VIN decoupling cap value2020-04-27T16:11:57ZTomasz WlostowskiIC8 VIN decoupling cap valueFrom Christos.
About the decoupling cap at the VIN pin of IC8, the datasheet mentions a value between 1uF and
4.7uF. I don't think that 22uF would actually be a problem but I thought it was worth a mention.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/46LDO Soft-start time is set to 1s, is such a long time intentional?2020-04-27T17:00:38ZTomasz WlostowskiLDO Soft-start time is set to 1s, is such a long time intentional?Reported by Christos. As in the title.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/45AFPGA_1V0: mixed-up LDO feedback dividers2020-04-27T15:01:28ZTomasz WlostowskiAFPGA_1V0: mixed-up LDO feedback dividers**From Christos:**
There's been a mixup with the LDO resistor dividers: the 1.0V one actually sets it for 1.2V, and
the 1.2V LDO is set for 1.05V, according to the datasheetReady for PCB layout review.https://ohwr.org/project/svec7/issues/41Perform test synthesis/P&R with the new pin assignment2020-04-20T16:10:26ZTomasz WlostowskiPerform test synthesis/P&R with the new pin assignmentDL: Have you tried this pin mapping and IO standards in ISE and Vivado?Ready for PCB layout review.Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec7/issues/40Documentation-related issues2020-07-02T14:37:32ZTomasz WlostowskiDocumentation-related issuesCommon thread for all coding style and documentation-related issues:
**Reported by Maciek Lipinski:**
- Some text is upside down, correct
- Update description (right bottom corner) on pages 17-21
- FMC slot 1, green letters indicating connectors are incorrect for
"I" and "J", should be "J" and "K" instead, the same problem with
connector names J2I and J2J, should be J2J and J2K (pdf page 5,
sheet 10)
- FMC slot 2, ideally, the naming of connectors would be consistent, i.e.
replace "J3D", "J3C", "J3B", and "J3A" with "J3H", "J3G", "J3B" and
"J3A". (pdf page 5, sheet 10)
**Reported by Dimitris Lampridis:**
General:
- On all pages, fix template info at bottom right. Project name, page description, EDA number,
people, dates, etc.
- The following pages use a different (and empty) template as well:
- DDR3 SODIMM
- AFPGA_FMC1_FMC2
- Slow_IO_Mux
- AFPGA_MISC
- AFPGA_1V0
- Fix the warnings reported by Altium after compilation (very few, nice!). If any is acceptable,
use a targeted no-ERC directive.
- Is there any particular reason why some nets have labels and others don't?
Top-level schematic:
- For the serial interface between the FPGAs, put a red "title" in the SFPGA block and change the
"user switches" red title in the AFPGA block to something meaningful. I also guess that the
rogue "user switches" red title at 4700,3700mil is from the SFPGA block.
- In the serial interface between FPGAs the _I and _O suffixes (and the whole RX/TX) on the net
labels are confusing. I would go for something explicit like bridge_s2a_dat, bridge_a2s_dat and
bridge_a2s_clk or something similar. I would use the same scheme in the HDL of both FPGAs as
well (with _i and _o in those).
- some diff signals have the differential directive on the top-level, others don't (they have it
inside some sheet of course). I'd prefer to stick with one approach, either all on the top
level, or all at the source (or all at the destination).
- I would use more harnesses, especially for things like the two identical sets of FMC signals
between AFPGA <-> FMC slots <-> GTP.
- I would rearrange the sheets and connections so that the Front Panel and FMC slots are the last
blocks on the right side of the page, with ports only on the left side of these sheet
symbols. It makes sense (to me at least): from VME on the left, through VME buffers, FPGAs, to
the front panel and FMC slots on the right.
- I would "hide" the FPGA power sheets under their respective FPGA top-level sheets. After all,
they are pins/sub-parts of the FPGA.
- Is there any particular reason why some nets have labels and others don't?
AFPGA:
- It would be nice to mention the FPGA banks used in each sheet symbol here, as well as the VCCIO
of each bank.
DDR3 SODIMM:
- Several DDR signals are active-low but their net labels lack the _N suffix.
- It is not immediately clear if SK1A is the top or bottom row of the DIMM socket.
- Also it is weird that a) we have two symbols, IC24 and SK1, with IC24 exactly on top of SK1 and
b) IC24 has no pins but all the signal names, while SK1 is the opposite.
- Missing differential directives on diff pairs
- Rename sheet to show that the bridge signals are also here.
- Missing no ERC on SODIMM CK1 pins.
AFPGA FMC1 FMC2:
- Any particular reason that the FMC pin order and slots are mixed? Does it help with layout?
Slow I/O Mux;
- This IMHO should be hierarchically "under" the AFPGA Misc sheet, not on the same level as the
other AFPGA sheets, because it does not contain any FPGA bank on itself and its ports would be
better grouped together with those of the AFPGA Misc sheet (e.g. the "FMC1 & FMC2" ports could
join the "FMC1" and "FMC2" port groups in the AFPGA Misc sheet symbol).
AFPGA Misc:
- Use capital letters for all ports
FPGA GTP:
- I would put the Kintex7 banks 115 and 116 hierarchicaly under the AFPGA sheet.
JTAG & SFPGA Flash:
- Rename sheet to remove the "SFPGA" from it, this now also has the AFPGA config.
- I would put the Kintex7 bank 0 hierarchicaly under the AFPGA sheet.
**Reported by Christos Gentsos:**
General:
- Page info has been left outdated, in some pages it's unpopulated
DDR3_SODIMM:
- The net DDR3_RESET should be renamed to DDR3_RESET_N, it's active low. Also assuming that it's
tied low to keep the RAM asleep until the FPGA is up and running?
- RAS/CAS/CS/WE signals are always low so there's no confusion but maybe their nets should get the _N,
too, for consistency
Slow_IO_MUX:
- The IOEXP_CLK_INH and IOEXP_SH/LD ports could be moved to the component above to slightly improve
readability
AFPGA_Misc:
- There are many nets that are labeled while only connected to hierarchical ports; the labels could
be removed for less clutter
JTAG chain + SFPGA flash
- It might be a good idea to move AFPGA above SFPGA, since it comes first in the JTAG chain.
VME_connectors
- Plenty of active-low signals are missing the _N but I don't know this isn't common notation in
this specific case, just noting
**Reported by Tom:**
- SFP port (113) names don't match with the FPGA GTX transceiver quad (115)
- Be consistent with IC names (ICxx or Uxx, we prefer ICxx).
- BOOT_CW port/BOOT_SW signal - keep the naming consistent.
Ready for PCB layout review.Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/38DDR3 swapped2020-04-27T14:55:06ZMattia RizziDDR3 swappedFrom the schematics, DDR3 should be swapped, so that IC24A match SK1AReady for PCB layout review.