Simple VME FMC Carrier 7 - SVEC7 issueshttps://ohwr.org/project/svec7/issues2020-04-27T14:26:36Zhttps://ohwr.org/project/svec7/issues/60Bypass caps in FT42322020-04-27T14:26:36ZTomasz WlostowskiBypass caps in FT4232FT4232: should we have some extra bypass capacitors on VCORE pins?Ready for PCB layout review.https://ohwr.org/project/svec7/issues/59VAdj PSU should be controlled by the AFPGA2020-04-27T14:46:12ZTomasz WlostowskiVAdj PSU should be controlled by the AFPGAConnect PS_FMC_2V5, PS_FMC_3V3 and PS_FMC_EN_VADJ to the AFPGA. The SFPGA doesn't have the access to the FMC EEPROMs so it can't know anyway how to configure the Vadj voltage.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/56Clocking: consider removing IC20 and SFP_CLK?2020-04-27T15:43:15ZTomasz WlostowskiClocking: consider removing IC20 and SFP_CLK?Many years ago (around 2010) we had a plan to develop a special copper SFP that would use the 125 MHz PLL clock for fully synchronous operation... We've never done that, so it's safe to say after 10 years this circuit will not be used.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/55Clocking: remove PLLFMC1_CLK/PLLFMC2_CLK.2020-04-27T16:01:07ZTomasz WlostowskiClocking: remove PLLFMC1_CLK/PLLFMC2_CLK.After a quick discussion (thanks Erik!) we concluded it was added for historical compatibility with the VFC card and never used in practice. It's safe to remove it (including the UFL and P2 connections).
------------ old message ----------
CERNies, does anybody remember why these lines were added in the original SVEC design (asking because we can't have both LVPECL and LVDS outputs in the CDCM61004 and these lines have fixed LVPECL bias resistors)?
Ready for PCB layout review.https://ohwr.org/project/svec7/issues/54Clocking: Kintex-7 doesn't support LVPECL.2020-09-24T14:11:42ZTomasz WlostowskiClocking: Kintex-7 doesn't support LVPECL.Both CDCM61004 PLLs are configure for LVPECL outputs. Kintex-7 does not support 'native' LVPECL anymore - so we either need the clocks to be AC-coupled (+ level translated) or change to LVDS.
see: https://forums.xilinx.com/t5/Other-FPGA-Architecture/Does-kintex7-support-LVPECL-in-HR-bank/td-p/638212Ready for PCB layout review.https://ohwr.org/project/svec7/issues/53IC4C: swapped Flash_MISO and Flash_MOSI lines.2020-04-27T16:02:30ZTomasz WlostowskiIC4C: swapped Flash_MISO and Flash_MOSI lines.Also make sure MISO/MOSI labels on the nets are consistent with the names of the pins...Ready for PCB layout review.https://ohwr.org/project/svec7/issues/52Question about I/O expander connection2020-04-27T16:33:23ZTomasz WlostowskiQuestion about I/O expander connectionIs there a reason for connecting U1-1 (input shift register cascade input) with the serial output of the output shift register (IC41-9)?Ready for PCB layout review.Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/51Pulldowns missing on IOEXP_RCLK and IOEXP_RESET2020-04-27T16:48:25ZTomasz WlostowskiPulldowns missing on IOEXP_RCLK and IOEXP_RESETConsider adding strong pulldowns (say, 1k) on IOEXP_RCLK and IOEXP_RESET. The I/O expanders should drive default values (0) when the AFPGA is unprogrammed.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/50Do we need voltage translation to Vadj_FMC for FMC JTAG and I2C?2020-04-20T21:59:43ZTomasz WlostowskiDo we need voltage translation to Vadj_FMC for FMC JTAG and I2C?Reported by Christos.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/49Use CERN library components2020-07-19T10:40:55ZTomasz WlostowskiUse CERN library componentsReported by Christos:
- SN74LV166ANSR is not taken from the CERN Altium library.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/48CDCM61004 VCCVCO connection2020-04-27T16:06:04ZTomasz WlostowskiCDCM61004 VCCVCO connectionFrom Christos.
According to the datasheet, VCCVCO is to be tied to VCCPLL1 and VCCPLL2, and VCCIN to VCCOUT. Here
(and in existing designs so it's definitely not grave, perhaps sub-optimal?), VCCVCO goes with
VCCIN and VCCOUT.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/47IC8 VIN decoupling cap value2020-04-27T16:11:57ZTomasz WlostowskiIC8 VIN decoupling cap valueFrom Christos.
About the decoupling cap at the VIN pin of IC8, the datasheet mentions a value between 1uF and
4.7uF. I don't think that 22uF would actually be a problem but I thought it was worth a mention.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/46LDO Soft-start time is set to 1s, is such a long time intentional?2020-04-27T17:00:38ZTomasz WlostowskiLDO Soft-start time is set to 1s, is such a long time intentional?Reported by Christos. As in the title.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/45AFPGA_1V0: mixed-up LDO feedback dividers2020-04-27T15:01:28ZTomasz WlostowskiAFPGA_1V0: mixed-up LDO feedback dividers**From Christos:**
There's been a mixup with the LDO resistor dividers: the 1.0V one actually sets it for 1.2V, and
the 1.2V LDO is set for 1.05V, according to the datasheetReady for PCB layout review.https://ohwr.org/project/svec7/issues/38DDR3 swapped2020-04-27T14:55:06ZMattia RizziDDR3 swappedFrom the schematics, DDR3 should be swapped, so that IC24A match SK1AReady for PCB layout review.https://ohwr.org/project/svec7/issues/37TPS74401RGWT bias2020-04-27T16:37:04ZMattia RizziTPS74401RGWT biasAffected: IC19, IC34
Connect Bias pin to P5V or something greater than 2.3V.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/36P1V0 considerations2020-04-27T15:34:46ZMattia RizziP1V0 considerations**From Mattia:**
Not sure about the scope of the ferrite bead(s):
- If the scope is to clean-up the dc/dc ripple, it will do little.
- If it's to limit the noise from FPGA VCCINT (1.0V) consumption, it's not a good idea. I would keep a very low inductance connection to the VRM due to the very high dynamic current that FPGA requires on VCCINT.
**From Christos:**
- Does the 0R resistor at SENSE+ serve a purpose or could it be replaced with a net tie?
- Small dips in VCCBRAM can cause hard-to-trace bugs, is there a reason we take our SENSE from
before the filtering and not near the load, which might offer improved regulation?
Ready for PCB layout review.https://ohwr.org/project/svec7/issues/35VP_0 and VN_02020-04-27T15:20:26ZMattia RizziVP_0 and VN_0Connect to GND according to the XADC User Guide pg 14:
http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
"This pin should be connected to GND if not used."Ready for PCB layout review.https://ohwr.org/project/svec7/issues/34sfpga: read dtack2020-07-12T10:58:12ZTristan Gingoldsfpga: read dtackIt would be nice if the sfpga could read the current dtack value from the VME bus (even when it doesn't drive it).
The purpose is to be able to spy or analyze the VME bus.
Bonus point if retry and berr could also be read.Ready for PCB layout review.Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/33Add serial EEPROM that are preprogrammed with MAC address2020-04-27T15:06:59ZErik van der BijAdd serial EEPROM that are preprogrammed with MAC addressConsider adding the same Serial EEPROMs as those used on the [SPEC7](https://www.ohwr.org/project/spec7/wikis) to have always a MAC address on the card:
- 2x 2K (128 x 8-bit) I2C Serial EEPROM (24AA025E48) which provides EUI-48
- one for APU MAC address
- one for WR MAC addressReady for PCB layout review.Michal GaskaMichal Gaska