Simple VME FMC Carrier 7 - SVEC7 issueshttps://ohwr.org/project/svec7/issues2020-09-24T14:11:42Zhttps://ohwr.org/project/svec7/issues/54Clocking: Kintex-7 doesn't support LVPECL.2020-09-24T14:11:42ZTomasz WlostowskiClocking: Kintex-7 doesn't support LVPECL.Both CDCM61004 PLLs are configure for LVPECL outputs. Kintex-7 does not support 'native' LVPECL anymore - so we either need the clocks to be AC-coupled (+ level translated) or change to LVDS.
see: https://forums.xilinx.com/t5/Other-FPGA-Architecture/Does-kintex7-support-LVPECL-in-HR-bank/td-p/638212Ready for PCB layout review.https://ohwr.org/project/svec7/issues/96Diff pairs impedance2020-08-13T08:34:13ZEvangelia GousiouDiff pairs impedanceThere could be some impedance issues; pictures below:
![Top](/uploads/1b0a82702db3e3b7438301b6a9491b84/Top.png)
![L3](/uploads/e5f1fc9f82e5f68ab9f745d6b502d34c/L3.png)
![L5](/uploads/3b70eda323c2fadd626c2b0e3c2dc978/L5.png)
![L6](/uploads/4dad10c9431c2501fb807b97b0c54234/L6.png)
![L8](/uploads/860910d7fac23d94f6308f067dde1f0e/L8.png)
![Bottom](/uploads/0b2620b21d1392864d14cedabea31010/Bottom.png)Ready for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/89FMC LA should be length matched2020-07-22T14:47:40ZGrzegorz DanilukFMC LA should be length matchedcurrently for example: FMC1_LA_33 is 3849mil vs FMC1_LA0 is 2568milReady for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/94PCB version2020-07-19T10:34:58ZEvangelia GousiouPCB versionOn the pcbrev pins it seems like v2; the silkscreen says v1; the edms number mentions v3Ready for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/51Pulldowns missing on IOEXP_RCLK and IOEXP_RESET2020-04-27T16:48:25ZTomasz WlostowskiPulldowns missing on IOEXP_RCLK and IOEXP_RESETConsider adding strong pulldowns (say, 1k) on IOEXP_RCLK and IOEXP_RESET. The I/O expanders should drive default values (0) when the AFPGA is unprogrammed.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/36P1V0 considerations2020-04-27T15:34:46ZMattia RizziP1V0 considerations**From Mattia:**
Not sure about the scope of the ferrite bead(s):
- If the scope is to clean-up the dc/dc ripple, it will do little.
- If it's to limit the noise from FPGA VCCINT (1.0V) consumption, it's not a good idea. I would keep a very low inductance connection to the VRM due to the very high dynamic current that FPGA requires on VCCINT.
**From Christos:**
- Does the 0R resistor at SENSE+ serve a purpose or could it be replaced with a net tie?
- Small dips in VCCBRAM can cause hard-to-trace bugs, is there a reason we take our SENSE from
before the filtering and not near the load, which might offer improved regulation?
Ready for PCB layout review.https://ohwr.org/project/svec7/issues/59VAdj PSU should be controlled by the AFPGA2020-04-27T14:46:12ZTomasz WlostowskiVAdj PSU should be controlled by the AFPGAConnect PS_FMC_2V5, PS_FMC_3V3 and PS_FMC_EN_VADJ to the AFPGA. The SFPGA doesn't have the access to the FMC EEPROMs so it can't know anyway how to configure the Vadj voltage.Ready for PCB layout review.