Simple VME FMC Carrier 7 - SVEC7 issueshttps://ohwr.org/project/svec7/issues2020-07-22T14:47:40Zhttps://ohwr.org/project/svec7/issues/89FMC LA should be length matched2020-07-22T14:47:40ZGrzegorz DanilukFMC LA should be length matchedcurrently for example: FMC1_LA_33 is 3849mil vs FMC1_LA0 is 2568milReady for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/90FMC DP should be length matched2020-08-20T09:00:52ZGrzegorz DanilukFMC DP should be length matchedcurrently for example: FMC1_DP3C2M is 2817mil vs FMC1_DP0C2M is 1805milReady for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/96Diff pairs impedance2020-08-13T08:34:13ZEvangelia GousiouDiff pairs impedanceThere could be some impedance issues; pictures below:
![Top](/uploads/1b0a82702db3e3b7438301b6a9491b84/Top.png)
![L3](/uploads/e5f1fc9f82e5f68ab9f745d6b502d34c/L3.png)
![L5](/uploads/3b70eda323c2fadd626c2b0e3c2dc978/L5.png)
![L6](/uploads/4dad10c9431c2501fb807b97b0c54234/L6.png)
![L8](/uploads/860910d7fac23d94f6308f067dde1f0e/L8.png)
![Bottom](/uploads/0b2620b21d1392864d14cedabea31010/Bottom.png)Ready for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/94PCB version2020-07-19T10:34:58ZEvangelia GousiouPCB versionOn the pcbrev pins it seems like v2; the silkscreen says v1; the edms number mentions v3Ready for V1 prototypeMichal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/55Clocking: remove PLLFMC1_CLK/PLLFMC2_CLK.2020-04-27T16:01:07ZTomasz WlostowskiClocking: remove PLLFMC1_CLK/PLLFMC2_CLK.After a quick discussion (thanks Erik!) we concluded it was added for historical compatibility with the VFC card and never used in practice. It's safe to remove it (including the UFL and P2 connections).
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CERNies, does anybody remember why these lines were added in the original SVEC design (asking because we can't have both LVPECL and LVDS outputs in the CDCM61004 and these lines have fixed LVPECL bias resistors)?
Ready for PCB layout review.https://ohwr.org/project/svec7/issues/56Clocking: consider removing IC20 and SFP_CLK?2020-04-27T15:43:15ZTomasz WlostowskiClocking: consider removing IC20 and SFP_CLK?Many years ago (around 2010) we had a plan to develop a special copper SFP that would use the 125 MHz PLL clock for fully synchronous operation... We've never done that, so it's safe to say after 10 years this circuit will not be used.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/48CDCM61004 VCCVCO connection2020-04-27T16:06:04ZTomasz WlostowskiCDCM61004 VCCVCO connectionFrom Christos.
According to the datasheet, VCCVCO is to be tied to VCCPLL1 and VCCPLL2, and VCCIN to VCCOUT. Here
(and in existing designs so it's definitely not grave, perhaps sub-optimal?), VCCVCO goes with
VCCIN and VCCOUT.Ready for PCB layout review.https://ohwr.org/project/svec7/issues/33Add serial EEPROM that are preprogrammed with MAC address2020-04-27T15:06:59ZErik van der BijAdd serial EEPROM that are preprogrammed with MAC addressConsider adding the same Serial EEPROMs as those used on the [SPEC7](https://www.ohwr.org/project/spec7/wikis) to have always a MAC address on the card:
- 2x 2K (128 x 8-bit) I2C Serial EEPROM (24AA025E48) which provides EUI-48
- one for APU MAC address
- one for WR MAC addressReady for PCB layout review.Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/34sfpga: read dtack2020-07-12T10:58:12ZTristan Gingoldsfpga: read dtackIt would be nice if the sfpga could read the current dtack value from the VME bus (even when it doesn't drive it).
The purpose is to be able to spy or analyze the VME bus.
Bonus point if retry and berr could also be read.Ready for PCB layout review.Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/2Use FT2232 instead of CP21032020-02-25T08:53:45ZMikolaj SowinskiUse FT2232 instead of CP2103If FT2232 is used instead of CP2103 it can be used both as USB-Serial and JTAG for programming FPGA (OpenOCD supports it).
[Kasli](https://github.com/sinara-hw/Kasli) can be used as a reference design.Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/12FPGA Bank Assignment2020-02-19T10:36:07ZMikolaj SowinskiFPGA Bank Assignment![image](/uploads/747417095ce9d81216fad2fcb70b209f/image.png)
![image](/uploads/8ee416c4b441422e3de8f1e19632c9c9/image.png)
Notes:
* Swapping within banks (14, 16) and (12, 13, 15) is allowed, except for the clock lines or signals connected to
global/regional clock input.
* Swapping in the DDR3 bank is allowed within byte groups (i.e. within DQ[0..7], DQ[8..15] etc)Ready for schematic review (CTI internal)Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/11GTX Transcivers mapping2020-02-12T08:19:37ZMikolaj SowinskiGTX Transcivers mapping![image](/uploads/cf520e6f9eed059950bbfa15bfbab33e/image.png)
Notes:
- GTX bank swapping is permitted (confirm this with CERN during layout to check if P&R is happy)
- GTX intra-bank clock and channel swapping is permitted (confirm, please)Ready for schematic review (CTI internal)Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/10FMC Connectors2020-02-19T10:35:08ZMikolaj SowinskiFMC ConnectorsReplace FMC1 connector with a HPC connector. Allocate 4 GTX channels to FMC1 HPC gigabit pins.Ready for schematic review (CTI internal)Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/9Power supply2020-03-23T10:04:16ZMikolaj SowinskiPower supply* [x] Put a load switch on +3.3V and +12V on both FMC slots allowing the FPGA to switch on/off the payload FMC
voltages. Each voltage has to be controlled separately (2 enable lines).
* [x] Allow adjusting IC9 regulator output voltages and on/off state, the voltage has to be controlled from the
AFPGA. The user should be able to choose the Vadj from the set of predefined values: +1.8V, +2.5V, +3.3V. By
default Vadj should be OFF. Both slots share the same Vadj.
* [x] Adapt supply voltages for the Kintex-7 FPGA (1.0 Vcore/1.2V VGtx)Ready for schematic review (CTI internal)Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/8Slow I/O2020-02-19T10:35:28ZMikolaj SowinskiSlow I/OIn order to further reduce the number of required pins in the AFPGA, some of the slow I/Os of the SVEC will be
moved to an I/O expander. Use the 74LV595/74LV166 shift registers as the I/O expanders an connect them to
the the [ioexp_ pins](https://www.ohwr.org/project/svec/blob/tom-svec7-test/hdl/syn/common/svec7/svec7.xdc#L641) of the AFPGA.
![image](/uploads/5b308c2b5cba595b8786102370ea0977/image.png)
![image](/uploads/6696346ae4df28df4a012f4264507bc5/image.png)Ready for schematic review (CTI internal)Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/6Flash memory2020-03-01T18:25:46ZMikolaj SowinskiFlash memoryAdd a separate flash for bitstream storage for the AFPGA connected to Xilinx’s boot SPI interface. This flash
must be also connected to the SFPGA, so that the bootloader can access it.Ready for schematic review (CTI internal)Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/5Change the DDR memory to a DDR SO-DIMM module socket (no ECC)2020-02-19T10:35:53ZMikolaj SowinskiChange the DDR memory to a DDR SO-DIMM module socket (no ECC)- Use pin assignment [here](https://www.ohwr.org/project/svec/blob/tom-svec7-test/hdl/syn/common/svec7/ddr.xdc).
- Can pin swap data pins within the byte groups.
- Connect the SPD I2C interface to a 3.3V bank (see the [constraint files](https://www.ohwr.org/project/svec/blob/tom-svec7-test/hdl/syn/common/svec7/svec7.xdc#L680))
Ready for schematic review (CTI internal)Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/4Remove the discrete DDR chips (IC28, IC4)2020-02-10T08:32:33ZMikolaj SowinskiRemove the discrete DDR chips (IC28, IC4)Ready for schematic review (CTI internal)Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/3Remove J1 and J16 (stand-alone power port)2020-07-02T14:38:43ZMikolaj SowinskiRemove J1 and J16 (stand-alone power port)Ready for schematic review (CTI internal)Michal GaskaMichal Gaskahttps://ohwr.org/project/svec7/issues/1Change the FPGA to XC7K160T-2FBG6762020-02-25T08:54:20ZMikolaj SowinskiChange the FPGA to XC7K160T-2FBG676Ready for schematic review (CTI internal)Michal GaskaMichal Gaska