Commit 2978372f authored by Michal Gaska's avatar Michal Gaska

replaced DP connectors

parent fea68e62
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......@@ -140,7 +140,7 @@ GenerateClassCluster=0
DocumentUniqueId=PSSLLKDJ
[Document7]
DocumentPath=Schematics\JTAG chain + SFPGA flash.SchDoc
DocumentPath=Schematics\JTAG chain + flash.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
......@@ -513,6 +513,23 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=BQEHIHPV
[Document29]
DocumentPath=SVEC.Annotation
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[Configuration1]
Name=Default Configuration
ParameterCount=0
......
......@@ -10,7 +10,7 @@ Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_ClkGeneration|Sch
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_FmcConnectors|SchDesignator=U_FmcConnectors|FileName=FMC_connectors.SchDoc|SymbolType=Normal|RawFileName=FMC_connectors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_fpga_gtp|SchDesignator=U_fpga_gtp|FileName=FPGA_GTP.SchDoc|SymbolType=Normal|RawFileName=FPGA_GTP.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_FrontPanel|SchDesignator=U_FrontPanel|FileName=Front_panel.SchDoc|SymbolType=Normal|RawFileName=Front_panel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_JTAG Chain + SFPGA Flash|SchDesignator=U_JTAG Chain + SFPGA Flash|FileName=JTAG Chain + SFPGA Flash.SchDoc|SymbolType=Normal|RawFileName=JTAG Chain + SFPGA Flash.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_JTAG Chain + Flash|SchDesignator=U_JTAG Chain + Flash|FileName=JTAG Chain + flash.SchDoc|SymbolType=Normal|RawFileName=JTAG Chain + flash.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_PowerSupplies|SchDesignator=U_PowerSupplies|FileName=Power_supplies.SchDoc|SymbolType=Normal|RawFileName=Power_supplies.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_SFPGA|SchDesignator=U_SFPGA|FileName=SFPGA.SchDoc|SymbolType=Normal|RawFileName=SFPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_SFPGA_power|SchDesignator=U_SFPGA_power|FileName=SFPGA_power.SchDoc|SymbolType=Normal|RawFileName=SFPGA_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
......
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