Frequently Asked Questions
Hardware
Q: Is there a users manual available?
A: A Hardware manual has been written by Janz Tec that shows clearly the block diagram and pinout of all connectors.
The best starting points for additional information are:
- Main features list
- Official production documentation: EDA-02530 (schematics, PCB layout)
- Software (pointing to examples of the production test software and firmware)
- VME64x core bus interface
- Mezzanine projects that use the SVEC as carrier board: fmc-delay-1ns-8cha, fmc-tdc, fmc-adc-100m14b4cha
- Other FAQ questions: Is there a FPGA reference design available?
- The somewhat similar SPEC board and its FAQ
Q: Does any FMC card work on the SVEC?
A: No, you cannot use any FMC card. The FMC standard allows many options
in the use of the signals on the FMC connector. Signalling levels,
differential or single ended signals and the level of Vadj may all be
chosen rather freely. And of course there is the major option of using a
High Pin-Count (HPC) or Low Pin-Count (LPC) connector which has, indeed,
less pins than the HPC.
To make the SVEC design simple, we had to make some design choices that
may make it not be compatible the FMC mezzanines you'd like to use.
Notably:
- The card uses an LPC connector.
- Vadj is fixed to 2.5 Volt, i.e. the signalling levels are 2.5V LVTTL.
- FMC connectivity: all 34 differential pairs connected, 1 GTP transceiver with clock, 2 clock pairs, JTAG.
To fully check for compatibility the best thing is to verify, signal by signal, the connections in the schematic of the SVEC and of the mezzanine you want to use. You may let us know once you've done this excercise for a particular mezzanine and we possibly can add it to a list of compatible mezzanines.
Q: Does the SVEC work in a 'classic' VME crate as opposed to a VME64x crate?
A: No, the SVEC does not work in a classic VME crate. Notably the 3V3 supply is taken from the D-row of the connector. The D and Z rows are the additional rows that are added on the VME64x connector. These two rows do not exist in the classic VME specification. Actually a classic VME crate does not have a 3V3 supply at all.
Gateware
Q: Is the FPGA programmable from the JTAG header on the board?
A: Yes, both FPGAs are programmable from the JTAG header on the board. After powering down you will loose the configuration.
With this same JTAG header you can also program the Configuration EEPROM
that is connected to the "system FPGA", so that the "system FPGA" can
start up with the firmware that is preloaded into the EEPROM.
The "system FPGA" firmware allows access to the EEPROM from the VME and
also to load the "application FPGA" with a firmware located in the
EEPROM. See the
svec-gateware-manual for details.
Actually the board will be delivered with the "system FPGA" EEPROM pre-loaded with a VME bus interface (the bootloader). With a program writing over the VME bus one is able to program the "application FPGA" who would then take over the control of the VME bus and disable the "system FPGA".
- Schematics at Project information -> Official production documentation.
- Tool for flashing over VME
svec-gateware-manual
Q: How do I generate the .mcs file that is described in theA: The IMPACT flasher needs an Intel HEX-formatted file as .mcs. You can prepare the MCS file from the binary flash image by using "Create PROM File" flow in Impact and clicking through all the wizards (the flash type is M25P128) or by using Xilinx's promgen tool directly:
promgen -p mcs -o image.mcs -spi -data_file up 0 image.bin -w
where image.bin is the binary file made by following the steps from section 4.5.1 of the Gateware Manual.
Q: Is there a FPGA reference design available?
A: We have not yet a fully documented reference design. However, the "Golden bitstream" is a good start. This is the code that will be loaded in the "application FPGA" and that is able to read the I2C bus on the mezzanines. For the "system FPGA" you may look at the bootloader
- SVEC Gateware Manual
- Golden bitstream VHDL code
- Bootloader VHDL code
- SVEC Gateware binaries
- All code at the SVEC Repository.
Q: What version of the Xilinx tools are you using?
A: We use Xilinx ISE. Currently versions 13.3 and 14.1 are working fine.
Q: The VME flasher utility says "the bootloader is too old".
A: It's probably right... The first version of the bootloader that was shipped with early series of the SVEC cards did not support booting the AFPGA from Flash and re-programming it through VME. This feature has been added in the second version of the bootloader. The instructions for updating are in the svec-gateware-manual
Q: In my system the extended pins (rows z and d) on connectors P1/P2 will be left unconnected. What to do?
A: Just don’t put these lines in the .ucf file and then the Xilinx tool will find a safe solution for these pins.
Q: Is it possible to simulate the project with Xilinx ISIM?
A: To that advantage of the SystemVerilog VME bus functional model, you need a simulator with SV support. Nevertheless, a VME testbench in vhdl is available (see hdl/sim/ddr_test/).
Q: Are all necessary files uploaded on the GIT repository?
A: The SVEC GIT repository relies on sub-modules. Therefore, you have to run the following commands (from the toplevel):
git submodule init
git submodule update
VME64x-core
Q: Can I use the SVEC with a VME core other than theA: Yes, just make sure the core is connected correctly: check VME I/O signals assignment, in particular the polarity of the buffer enable/direction signals. You may also have to install drivers specific to your VME core and operating system.
VmeIntfce
core used in many places at CERN?
Q: Is it possible use the SVEC with the A: Yes. In this case, do not install the SVEC driver and do not declare
the card as FMC-SVEC
in CCDB. You may use the svec-flasher
tool to
program the AFPGA flash or load the AFPGA bitstream from the command
line of the
frontend.
Q: Is there a command line tool for loading a bitstream to the AFPGA over VME (without rebooting the frontend)?
A: Yes, svec-flasher
can do it. Please read the section 4.2 of the
Gateware Manual for
instructions.
Q: Is there a possibility to determine (in software), whether the application FPGA is already loaded and configured or not?
A: The current bootloader version has no "direct" check for that. If the
AFPGA is already
programmed, the bootloader's CSRs are not visible and will throw a VME
bus error when read. If the bootloader is active (= AFPGA not
programmed),
reading the IDR register value (CR/CSR @ 0x7000C) will return 0x53564543
(SVEC signature in ASCII).
Erik van der Bij, Tom Wlostowski, Matthieu Cattin - 14 October 2015