3.0.0 - 2022-12-05
==================
Added
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- ci: better automation
- sw: support for Linux 5.10

Removed
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- hdl: unused and obsolete top-levels and simulations
- hdl: Xilinx chipscope for SFPGA (files were actually for AFPGA)

Changed
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- hdl: 'golden_wr' top-level renamed to 'wr_example'
- hdl: 'template' testbench now used for simulating the golden top-level
- sw|API change: the API to flash a bitstream moved from debugfs to sysfs. The
  Linux kernel community removed API we used. The same behavior was achievable
  only using sysfs.
- bld: improved Makefiles

Fixed
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- hdl: building of all top-levels
- hdl: missing ddr and wr-cores dependencies
- hdl: corrected and re-enabled timing constraints
- hdl: location of general-cores in rtl Manifest