PTS: timing violation in DAC signal.
See attached file
According to the Fig. 2 shown in the AD5662 datasheet, it is clear that
chip uses the negative clock
edge to latch the data, with a setup/hold time given by t5 and t6.
The PTS test used for the SVEC/SPEC board changes DAC DIN signal at exactly the falling SCLK
edge. Therefore, it violates the timing conditions indicated in the datasheet (setup time=5ns and hold
time=4.5ns) as shown in Figure 1.
This produces that voltage values written from Python code are wrong and do not correspond with the
real values presented at the DAC output (as measured with an oscilloscope).
Problem not urgent as the PTS basically only has to check if every solder connection is correctly done, even with the problem present, it will detect if the DAC would not be correctly connected.