Simple VME FMC Carrier SVEC issueshttps://ohwr.org/project/svec/issues2023-10-09T08:25:33Zhttps://ohwr.org/project/svec/issues/32V0 - Wrong name for 12V testpoint2023-10-09T08:25:33ZProjectsV0 - Wrong name for 12V testpoint12V testpoint is named "P12V VME" on the silkscreen.
Should be "P12V".https://ohwr.org/project/svec/issues/26V1 - various PCB layout issues2023-10-09T08:25:33ZErik van der BijV1 - various PCB layout issuesVarious PCB layout issues have been found, mostly related to
tolerances.
See attached Excel file.
### Files
* [0019-4929-1.xls](/uploads/6942a6013515fdb5191ff4be39c7b7d2/0019-4929-1.xls)https://ohwr.org/project/svec/issues/31V0 - Add SO16 footprint for FPGA config flash2023-10-09T08:25:33ZProjectsV0 - Add SO16 footprint for FPGA config flashCurrently the FPGA config flash (IC14) is in MPL8 package -\>
M25P128-VME6G
An alternative SO16 footprint should be added in order to overcome
supplier stock shortage.
So16 reference -\> M25P128-VMF6Ghttps://ohwr.org/project/svec/issues/20V2 - Front-panel BOM missing EMC Gasket. Change screw.2023-10-09T08:25:33ZErik van der BijV2 - Front-panel BOM missing EMC Gasket. Change screw.The [arrangement
BOM](https://edms.cern.ch/file/1249647/2/EDA-02530-V2-0_arrangement-mat.pdf)
is wrong:
It specifies
- ELMA 66-514-26 - EMC Front Panels - Aluminium With EMC Gasket acc.
IEEE - Thickness 2.5mm
- But this order number does *not* contain the EMC Gasket
- EMC Gasket needs to be ordered separately (ELMA 81-062-06)
<!-- end list -->
- Add EMC Gasket to BOM
- (while at it, also correct filename inside the BOM: arrangemet -\>
arrangement)
See also
- [ELMA
datasheet](http://www.elma.com/Admin/ProductionFiles//ProductTypeFile/919/English/IEC_Ergonomic_Handle_Total.pdf)Erik van der BijErik van der Bijhttps://ohwr.org/project/svec/issues/27V1 - GTP clock inverted2023-10-09T08:25:33ZTomasz WlostowskiV1 - GTP clock invertedThe reference clock for GTP 245 (part IC19L) is inverted on
FPGA\_GTP.SchDoc (FPGA\_PLL\_REF\_CLK0\_N port connected via C162 to
MGTREFCLK0P and vice versa).https://ohwr.org/project/svec/issues/30V1 - Review 12V generation schematics2023-10-09T08:25:33ZErik van der BijV1 - Review 12V generation schematicsThe step-up converter and associated components add many unique items to
the BOM.
- Review schematics design of 12V generation
- unique BOM items (unique valued resistors, non-generic 0.02 Ohm)
- why 2 power transistors in parallel
- Consider using a ready-made modulehttps://ohwr.org/project/svec/issues/17HDL: increase space for the AFPGA bitstream in the flash2022-12-05T15:07:08ZTomasz WlostowskiHDL: increase space for the AFPGA bitstream in the flashThe current version of the flash memory layout reserves too little space
for the AFPGA configuration bitstream (4 MB vs 4.04 MB).
Workaround: enable bitstream compression in ISE.Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/4DS locs are swapped in golden UCF2022-12-05T15:07:08ZTristan GingoldDS locs are swapped in golden UCFThe mapping of the VME\_DS\[1:0\] pins in the ucf file are swapped (wrt
the schema).
As a consequence, it may be swapped in many designs too (like wr-cores)
using svec.
(Bytes access look unused).Dimitris LampridisDimitris Lampridishttps://ohwr.org/project/svec/issues/16Reset CDCM61004 PLL on powerup2022-12-05T15:07:08ZTomasz WlostowskiReset CDCM61004 PLL on powerupRelated to issue \#894.
Pulse PLL\_CE pin low to reset the PLL some time after the startup of
the reference oscillator. This prevents the PLL from calibrating its VCO
with wrong reference clock and locking on incorrect frequency.Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/15V2 - Mini DisplayPort connector is obsolete2022-12-05T15:07:08ZProjectsV2 - Mini DisplayPort connector is obsoleteThe reference 64L020S-331N-B is no longer
manufactured:
http://uk.farnell.com/multicomp/64l020s-331n-b/receptacle-mini-dp-r-a-tht-30au/dp/1895014
### Files
* [MDPR-2020-BK63U1F.pdf](/uploads/5af3eea4399f2b2cb48f7645a59bd62d/MDPR-2020-BK63U1F.pdf)https://ohwr.org/project/svec/issues/7Gateware: missing support for hdlmake2022-12-05T15:07:08ZDimitris LampridisGateware: missing support for hdlmakeGolden AFPGA design does not support hdlmake (missing Manifest.py). It
only includes a hard-coded (and outdated) Xilinx project file.
Bootloader SFPGA design does not support newer versions of hdlmake.
Attached two patches to introduce full support for hdlmake.
### Files
* [0003-sfpga_bootloader-remove-Xilinx-ISE-project-file-and-.patch](/uploads/890a0b973465772d7aa6c20d3d56e884/0003-sfpga_bootloader-remove-Xilinx-ISE-project-file-and-.patch)
* [0002-golden-remove-Xilinx-ISE-project-file-and-introduce-.patch](/uploads/351b0f1b73fd6157c9804602f144c7a4/0002-golden-remove-Xilinx-ISE-project-file-and-introduce-.patch)Dimitris LampridisDimitris Lampridishttps://ohwr.org/project/svec/issues/61Bug in software/tools/vme-flasher/svec-flasher.c2022-11-10T07:39:21ZRené GeißlerBug in software/tools/vme-flasher/svec-flasher.c**This bug makes Flash programming fail on SVEC v3**
The reason is an incomplete initialization of the `sector_map` memory, which leeds to some Flash sectors not beeing erased before writing.
**Bugfix:**
change line 253 of software/tools/vme-flasher/svec-flasher.c
from:
`memset(sector_map, 0, sizeof(sector_map));`
to:
`memset(sector_map, 0, sizeof(int) * FLASH_SIZE / sector_size);`
**Explanation:**
`sizeof(sector_map)` returns the size of the pointer to the `sector_map`, not the size of the `sector_map` itself. This leads to an incomplete initialization.https://ohwr.org/project/svec/issues/58V0 - FMC Slot reference texts not aligned2019-02-12T10:10:19ZErik van der BijV0 - FMC Slot reference texts not alignedThe "FMC Slot 2” text is higher than “FMC Slot 1”. I.e. the baseline is
higher, or in other words, the text is further away from FMC connector.
The text font size is indeed the same.
- Align vertically baselines of texts
- Consider rotating this large text so the orientation is the same as
the other large texts.https://ohwr.org/project/svec/issues/57V0 - C175 too close to inductor2019-02-12T10:10:18ZErik van der BijV0 - C175 too close to inductorOSCON capacitor C175 is too close to inductor L14, T12 and D1. As these
components heat up, C175 may become too hot, notably in stand-alone
applications.
- Move C175 away.https://ohwr.org/project/svec/issues/56V0 - Silkscreen texts too small2019-02-12T10:10:18ZErik van der BijV0 - Silkscreen texts too smallTexts SFPGA PROGRAM and SFPGA INIT B on the silkscreen (near B4, B11 and
P1) is too small.
- Check why this is not found by a DRC.
- Correct text size.https://ohwr.org/project/svec/issues/55V0 - 3D model component too black2019-02-12T10:10:17ZErik van der BijV0 - 3D model component too blackThe 3D model of 50WQ06FNPbF in TO228P991X239-3N-R546X521 is too black
(see https://www.ohwr.org/1229)
I already asked the Design Office to correct the symbol.
- Replace symbol by the updated one from the Design Officehttps://ohwr.org/project/svec/issues/54V0 - Front panel not yet designed2019-02-12T10:10:16ZErik van der BijV0 - Front panel not yet designedThe front panel is not yet designed. Should be done by the Design Office
when making the V1.https://ohwr.org/project/svec/issues/53V0 - No easy way to store parameters for AFPGA2019-02-12T10:10:16ZErik van der BijV0 - No easy way to store parameters for AFPGAThe Application FPGA has now easy way to store application parameters
such as White Rabbit calibration parameters. Data can be stored in the
Configuration PROM, but can only be accessed via the System FPGA.
- Add EEPROM like used on Mezzanines (24AA64T-I/MC) and connect to
Application FPGAhttps://ohwr.org/project/svec/issues/52V0 - Clocks not conencted to global clock inputs.2019-02-12T10:10:15ZProjectsV0 - Clocks not conencted to global clock inputs.PLL\_2SFPGA\_P/N and VME\_SYSCLK are not connected to global clock input
of the FPGA\!https://ohwr.org/project/svec/issues/51V0 - P12V boost converter disabled by default2019-02-12T10:10:14ZProjectsV0 - P12V boost converter disabled by defaultPin 3 of the TPS40210 (IC18) must be pulled down in order to enable the
converter,
but it is pulled up via R60.
Pin 3 of the TPS40210 is internally pulled down.