Simple VME FMC Carrier SVEC issueshttps://ohwr.org/project/svec/issues2022-11-10T07:39:21Zhttps://ohwr.org/project/svec/issues/61Bug in software/tools/vme-flasher/svec-flasher.c2022-11-10T07:39:21ZRené GeißlerBug in software/tools/vme-flasher/svec-flasher.c**This bug makes Flash programming fail on SVEC v3**
The reason is an incomplete initialization of the `sector_map` memory, which leeds to some Flash sectors not beeing erased before writing.
**Bugfix:**
change line 253 of software/tools/vme-flasher/svec-flasher.c
from:
`memset(sector_map, 0, sizeof(sector_map));`
to:
`memset(sector_map, 0, sizeof(int) * FLASH_SIZE / sector_size);`
**Explanation:**
`sizeof(sector_map)` returns the size of the pointer to the `sector_map`, not the size of the `sector_map` itself. This leads to an incomplete initialization.https://ohwr.org/project/svec/issues/58V0 - FMC Slot reference texts not aligned2019-02-12T10:10:19ZErik van der BijV0 - FMC Slot reference texts not alignedThe "FMC Slot 2” text is higher than “FMC Slot 1”. I.e. the baseline is
higher, or in other words, the text is further away from FMC connector.
The text font size is indeed the same.
- Align vertically baselines of texts
- Consider rotating this large text so the orientation is the same as
the other large texts.https://ohwr.org/project/svec/issues/57V0 - C175 too close to inductor2019-02-12T10:10:18ZErik van der BijV0 - C175 too close to inductorOSCON capacitor C175 is too close to inductor L14, T12 and D1. As these
components heat up, C175 may become too hot, notably in stand-alone
applications.
- Move C175 away.https://ohwr.org/project/svec/issues/56V0 - Silkscreen texts too small2019-02-12T10:10:18ZErik van der BijV0 - Silkscreen texts too smallTexts SFPGA PROGRAM and SFPGA INIT B on the silkscreen (near B4, B11 and
P1) is too small.
- Check why this is not found by a DRC.
- Correct text size.https://ohwr.org/project/svec/issues/55V0 - 3D model component too black2019-02-12T10:10:17ZErik van der BijV0 - 3D model component too blackThe 3D model of 50WQ06FNPbF in TO228P991X239-3N-R546X521 is too black
(see https://www.ohwr.org/1229)
I already asked the Design Office to correct the symbol.
- Replace symbol by the updated one from the Design Officehttps://ohwr.org/project/svec/issues/54V0 - Front panel not yet designed2019-02-12T10:10:16ZErik van der BijV0 - Front panel not yet designedThe front panel is not yet designed. Should be done by the Design Office
when making the V1.https://ohwr.org/project/svec/issues/53V0 - No easy way to store parameters for AFPGA2019-02-12T10:10:16ZErik van der BijV0 - No easy way to store parameters for AFPGAThe Application FPGA has now easy way to store application parameters
such as White Rabbit calibration parameters. Data can be stored in the
Configuration PROM, but can only be accessed via the System FPGA.
- Add EEPROM like used on Mezzanines (24AA64T-I/MC) and connect to
Application FPGAhttps://ohwr.org/project/svec/issues/52V0 - Clocks not conencted to global clock inputs.2019-02-12T10:10:15ZProjectsV0 - Clocks not conencted to global clock inputs.PLL\_2SFPGA\_P/N and VME\_SYSCLK are not connected to global clock input
of the FPGA\!https://ohwr.org/project/svec/issues/51V0 - P12V boost converter disabled by default2019-02-12T10:10:14ZProjectsV0 - P12V boost converter disabled by defaultPin 3 of the TPS40210 (IC18) must be pulled down in order to enable the
converter,
but it is pulled up via R60.
Pin 3 of the TPS40210 is internally pulled down.https://ohwr.org/project/svec/issues/50V0 - R189, R1932019-02-12T10:10:13ZGrzegorz KasprowiczV0 - R189, R193wrong resistor values - instead 0R22(220mOhm) should be 0R022 (22mOhm)https://ohwr.org/project/svec/issues/49V0 - FMC step up gives 11.56V2019-02-12T10:10:12ZGrzegorz KasprowiczV0 - FMC step up gives 11.56Vthe DC/DC converter generates 11.56V instead of 12V. Trimming the output
voltage will probably need to add one more resistor value to the BOMhttps://ohwr.org/project/svec/issues/48V0 - No pullback on copper planes2019-02-12T10:10:12ZTomasz WlostowskiV0 - No pullback on copper planesThe internal copper planes are touching the very edge of the board (no
pullback / margin). This can cause short circuits with the crate.https://ohwr.org/project/svec/issues/47V0 - Missing ESD discharge copper on bottom2019-02-12T10:10:11ZProjectsV0 - Missing ESD discharge copper on bottomA part of the upper ESD discharge strip is missing on the bottom layer
(next to TP4).
This is due to an additional region for the power-SATA connector.https://ohwr.org/project/svec/issues/46V0 - LEDs silkscreen2019-02-12T10:10:11ZProjectsV0 - LEDs silkscreenSilkscreen with the LEDs meaning should be improved.
\-\> Make it bigger and inverted.https://ohwr.org/project/svec/issues/45V0 - LEMO 'ntny' connector type not easily available2019-02-12T10:10:10ZErik van der BijV0 - LEMO 'ntny' connector type not easily availableAbout the stacked LEMO connectors on the front-panel.
epy.00.250ntny is not easily available on the market. LEMO sells them,
but they are rather expensive.
epy.00.250ntn (without the 'y') is on stock, but is 1mm higher and would
not fit a VME panel.
O.B. is checking out with LEMO.Erik van der BijErik van der Bijhttps://ohwr.org/project/svec/issues/44V0 - eSATA connector too big for front panel2019-02-12T10:10:09ZProjectsV0 - eSATA connector too big for front panelFind a type of connector that fits on the front panel.
Two connectors are needed.https://ohwr.org/project/svec/issues/43V0 - Wrong pullups on VME address/data buffer enable lines2019-02-12T10:10:09ZTomasz WlostowskiV0 - Wrong pullups on VME address/data buffer enable linesThe current configuration of pullup/resistors on the VME buffer control
lines sets the default direction of FPGA-\>VME bus and disables the
buffer outputs. This is incompatible with applications that require
passive monitoring of VME accesses (i.e. bootloaders).
Changing the pullups to pulldowns will reverse the direction and enable
the buffers by default.
Components concerned: R157, R203, R316, R175.https://ohwr.org/project/svec/issues/42V0 - missing pulldown on VME_D_DIR signal2019-02-12T10:10:08ZTomasz WlostowskiV0 - missing pulldown on VME_D_DIR signalThe signal is floating when the FPGAs are not (yet) configured, causing
undefined direction of the VME data buffers. Add a pulldown resistor.https://ohwr.org/project/svec/issues/41V0 - R219/R220 too big, can't boot SFPGA from flash2019-02-12T10:10:07ZTomasz WlostowskiV0 - R219/R220 too big, can't boot SFPGA from flashR219/R220 (driving M0/M1 SFPGA pins) are too big and the SFPGA can't
boot up from flash. Replacing with 0-ohm fixes the problem.https://ohwr.org/project/svec/issues/40Clean-up git repo2019-02-12T10:10:07ZProjectsClean-up git repoAll SVFC files and directories should be removed from circuit\_board/