Simple VME FMC Carrier SVEC issueshttps://ohwr.org/project/svec/issues2022-01-25T07:48:44Zhttps://ohwr.org/project/svec/issues/60V3 - Replace DDR3 memory by DDR3 SO-DIMM module2022-01-25T07:48:44ZErik van der BijV3 - Replace DDR3 memory by DDR3 SO-DIMM module**Background**
- With the new 1/2GSPS 8-bit ADC mezzanines, the memory bandwidth of the two 16-bit DDR chips used currently on the SVEC carrier [1] is insufficient.
- Xilinx's DDR3 controller performance is quite low compared to alternatives.
- DDR3 chips are getting difficult to obtain.
**Tasks**
- Remove the two DDR3 chips from the SVEC.
- Connect a DDR3 SO-DIMM module socket instead with 64-bit data path width (some pin swapping/reassignment might be needed).
- Evaluate the performance of the LiteDRAM controller with AXI4-full host interface, port it to SVEC AFPGA and validate with the SO-DIMM module [1].
- Provide proof-of-concept VHDL/Verilog code.
[1] https://github.com/enjoy-digital/litedramEDA-02530-V4-0Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/59V3 - mini displayPort connector obsolete (J5, J9)2019-06-13T13:47:39ZErik van der BijV3 - mini displayPort connector obsolete (J5, J9)The mini displayPort connector (J5 and J9) is obsolete and the last production in 2018 had these removed (and the front-panel was redone without holes in these locations).
See if any alternative can be found for the GENESIS MDPR-2020-BK63U1F, which likely needs another footprint.EDA-02530-V4-0Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/29V1 - Uneven track width2019-06-13T13:47:39ZProjectsV1 - Uneven track widthSome tracks for similar signals (e.g. VME signals) have uneven track
width.
### Files
* [SVEC_track_width.jpg](/uploads/43d56f67f8170fb23bdfe5f4ee683007/SVEC_track_width.jpg)EDA-02530-V4-0Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/21V2 - Pullback on top and bottom layers is too small2019-06-13T13:47:39ZProjectsV2 - Pullback on top and bottom layers is too smallPullback on top and bottom layers (for ESD polygons) is 0.192mm and
should be at least 0.2mm
### Files
* [Screenshot-rdesktop_-_rdseda19.cern.ch-1.png](/uploads/d51211a3c99fa59cbb8511e857d525db/Screenshot-rdesktop_-_rdseda19.cern.ch-1.png)EDA-02530-V4-0Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/13V3 - Resistor settings show V2, not V32019-06-13T13:47:38ZErik van der BijV3 - Resistor settings show V2, not V3There are some resistors that should show which version of PCB is
used.
Unfortunately the settings on the V3 are the same as on the V2.
Not a problem as they are fully compatible.
Make sure new versions have the correct setting.EDA-02530-V4-0Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/12V3 - schematics: VMEPX_SERA and SERB shown, but not used2022-12-05T15:07:08ZErik van der BijV3 - schematics: VMEPX_SERA and SERB shown, but not usedThe VMEPX\_SERA and SERB on VME P1, pins B21 and B22 are shown on pages
18 and 19 of the schematics. But they are actually not used (they are
only connected on the P1 connector).
These are the serial I2C lines that are for example on an ELMA VME
crate. They cannot be used on the SVEC as they are not connected.
- Remove from schematics to remove confusion *or*
- Add a buffer and connect to Xilinx (cf. CONV-TTL-BLO) so that they
can used for stand-alone systems not requiring a processor with VME
busEDA-02530-V4-0Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/9V3 - debug LEDs ROHM SML-311UTT86K not available2022-12-05T15:07:08ZErik van der BijV3 - debug LEDs ROHM SML-311UTT86K not availableThe ten LEDs on the board, used for debugging (SML-311UTT86K) is not
available anymore.
The SML-311UTT86 would be the same LED but they have a difference in
brightness:
with K: 4.0 – 6.3 mcd at 2mA
without K: 0.9 – 2.5 mcd at 2mA
Suggest to replace
SML-311UTT86K by
SML-311UTT86
Problem and solution from Janz. Agreed with Erik.
LED type will be different on productions from August 2017 on.EDA-02530-V4-0Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/3V3 - SFP cage type is obsolete, EOL2022-12-05T15:07:07ZErik van der BijV3 - SFP cage type is obsolete, EOLThe two-piece SFP Cage from Tyco Electronics
([6367034-1](http://www.te.com/usa-en/search.html?q=6367034-1) and
[6367035-1](http://www.te.com/usa-en/search.html?q=6367035-1)) is at
End-of-Life (EOL).
The supplier suggests the use of the one-piece solution
[2227303-3](http://www.te.com/usa-en/product-2227303-3.html).
This solution will be used (with agreement from CERN) for new
productions by JanzTec from January 2018 on.
*Reported by JanzTec on 22/1/18.*EDA-02530-V4-0Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/2V3 - PCB and schematics wrong for use of optional USB - FTDI chip2022-12-05T15:07:08ZErik van der BijV3 - PCB and schematics wrong for use of optional USB - FTDI chipWhen the option for the USB - FTDI chip (FT2232HL) needs to be used, it
will not work. There is a problem that appears when the optional
components for this will be mounted.
See the attached image. Page 13 of the schematics shows that the line
connected on the left of R248 is called USB\_TMS (like the one connected
to R243). The line to R248 should be USB\_TDI.
Schematics at:
https://edms.cern.ch/file/1421529/1/EDA-02530-V3-0_sch.pdf (page 13)
*Problem reported by JanzTec (16/5/18)*
### Files
* [USB_TMSx2_bottom_one_wrong.png](/uploads/f4219c9bc8b7cf31cf94b81dfa26da77/USB_TMSx2_bottom_one_wrong.png)EDA-02530-V4-0Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/1V3 - D1 Shottky Diode Vishay 50WQ06FNPbF EOL, obsolete2022-12-05T15:07:08ZErik van der BijV3 - D1 Shottky Diode Vishay 50WQ06FNPbF EOL, obsoleteD1 1 60V 5.5A Schottky Rectifier 50WQ06FNPbF VISHAY SEMICONDUCTOR
50WQ06FNPbF is at EOL.
JanzTec recommends to replace by Vishay 50WQ06FN-M3 that has all the
same parameters. This will be used in the 2018 production run.EDA-02530-V4-0Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/61Bug in software/tools/vme-flasher/svec-flasher.c2022-11-10T07:39:21ZRené GeißlerBug in software/tools/vme-flasher/svec-flasher.c**This bug makes Flash programming fail on SVEC v3**
The reason is an incomplete initialization of the `sector_map` memory, which leeds to some Flash sectors not beeing erased before writing.
**Bugfix:**
change line 253 of software/tools/vme-flasher/svec-flasher.c
from:
`memset(sector_map, 0, sizeof(sector_map));`
to:
`memset(sector_map, 0, sizeof(int) * FLASH_SIZE / sector_size);`
**Explanation:**
`sizeof(sector_map)` returns the size of the pointer to the `sector_map`, not the size of the `sector_map` itself. This leads to an incomplete initialization.https://ohwr.org/project/svec/issues/58V0 - FMC Slot reference texts not aligned2019-02-12T10:10:19ZErik van der BijV0 - FMC Slot reference texts not alignedThe "FMC Slot 2” text is higher than “FMC Slot 1”. I.e. the baseline is
higher, or in other words, the text is further away from FMC connector.
The text font size is indeed the same.
- Align vertically baselines of texts
- Consider rotating this large text so the orientation is the same as
the other large texts.https://ohwr.org/project/svec/issues/57V0 - C175 too close to inductor2019-02-12T10:10:18ZErik van der BijV0 - C175 too close to inductorOSCON capacitor C175 is too close to inductor L14, T12 and D1. As these
components heat up, C175 may become too hot, notably in stand-alone
applications.
- Move C175 away.https://ohwr.org/project/svec/issues/56V0 - Silkscreen texts too small2019-02-12T10:10:18ZErik van der BijV0 - Silkscreen texts too smallTexts SFPGA PROGRAM and SFPGA INIT B on the silkscreen (near B4, B11 and
P1) is too small.
- Check why this is not found by a DRC.
- Correct text size.https://ohwr.org/project/svec/issues/55V0 - 3D model component too black2019-02-12T10:10:17ZErik van der BijV0 - 3D model component too blackThe 3D model of 50WQ06FNPbF in TO228P991X239-3N-R546X521 is too black
(see https://www.ohwr.org/1229)
I already asked the Design Office to correct the symbol.
- Replace symbol by the updated one from the Design Officehttps://ohwr.org/project/svec/issues/54V0 - Front panel not yet designed2019-02-12T10:10:16ZErik van der BijV0 - Front panel not yet designedThe front panel is not yet designed. Should be done by the Design Office
when making the V1.https://ohwr.org/project/svec/issues/53V0 - No easy way to store parameters for AFPGA2019-02-12T10:10:16ZErik van der BijV0 - No easy way to store parameters for AFPGAThe Application FPGA has now easy way to store application parameters
such as White Rabbit calibration parameters. Data can be stored in the
Configuration PROM, but can only be accessed via the System FPGA.
- Add EEPROM like used on Mezzanines (24AA64T-I/MC) and connect to
Application FPGAhttps://ohwr.org/project/svec/issues/52V0 - Clocks not conencted to global clock inputs.2019-02-12T10:10:15ZProjectsV0 - Clocks not conencted to global clock inputs.PLL\_2SFPGA\_P/N and VME\_SYSCLK are not connected to global clock input
of the FPGA\!https://ohwr.org/project/svec/issues/51V0 - P12V boost converter disabled by default2019-02-12T10:10:14ZProjectsV0 - P12V boost converter disabled by defaultPin 3 of the TPS40210 (IC18) must be pulled down in order to enable the
converter,
but it is pulled up via R60.
Pin 3 of the TPS40210 is internally pulled down.https://ohwr.org/project/svec/issues/50V0 - R189, R1932019-02-12T10:10:13ZGrzegorz KasprowiczV0 - R189, R193wrong resistor values - instead 0R22(220mOhm) should be 0R022 (22mOhm)