Simple VME FMC Carrier SVEC issueshttps://ohwr.org/project/svec/issues2022-12-05T15:07:08Zhttps://ohwr.org/project/svec/issues/1V3 - D1 Shottky Diode Vishay 50WQ06FNPbF EOL, obsolete2022-12-05T15:07:08ZErik van der BijV3 - D1 Shottky Diode Vishay 50WQ06FNPbF EOL, obsoleteD1 1 60V 5.5A Schottky Rectifier 50WQ06FNPbF VISHAY SEMICONDUCTOR
50WQ06FNPbF is at EOL.
JanzTec recommends to replace by Vishay 50WQ06FN-M3 that has all the
same parameters. This will be used in the 2018 production run.EDA-02530-V4-0Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/3V3 - SFP cage type is obsolete, EOL2022-12-05T15:07:07ZErik van der BijV3 - SFP cage type is obsolete, EOLThe two-piece SFP Cage from Tyco Electronics
([6367034-1](http://www.te.com/usa-en/search.html?q=6367034-1) and
[6367035-1](http://www.te.com/usa-en/search.html?q=6367035-1)) is at
End-of-Life (EOL).
The supplier suggests the use of the one-piece solution
[2227303-3](http://www.te.com/usa-en/product-2227303-3.html).
This solution will be used (with agreement from CERN) for new
productions by JanzTec from January 2018 on.
*Reported by JanzTec on 22/1/18.*EDA-02530-V4-0Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/9V3 - debug LEDs ROHM SML-311UTT86K not available2022-12-05T15:07:08ZErik van der BijV3 - debug LEDs ROHM SML-311UTT86K not availableThe ten LEDs on the board, used for debugging (SML-311UTT86K) is not
available anymore.
The SML-311UTT86 would be the same LED but they have a difference in
brightness:
with K: 4.0 – 6.3 mcd at 2mA
without K: 0.9 – 2.5 mcd at 2mA
Suggest to replace
SML-311UTT86K by
SML-311UTT86
Problem and solution from Janz. Agreed with Erik.
LED type will be different on productions from August 2017 on.EDA-02530-V4-0Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/12V3 - schematics: VMEPX_SERA and SERB shown, but not used2022-12-05T15:07:08ZErik van der BijV3 - schematics: VMEPX_SERA and SERB shown, but not usedThe VMEPX\_SERA and SERB on VME P1, pins B21 and B22 are shown on pages
18 and 19 of the schematics. But they are actually not used (they are
only connected on the P1 connector).
These are the serial I2C lines that are for example on an ELMA VME
crate. They cannot be used on the SVEC as they are not connected.
- Remove from schematics to remove confusion *or*
- Add a buffer and connect to Xilinx (cf. CONV-TTL-BLO) so that they
can used for stand-alone systems not requiring a processor with VME
busEDA-02530-V4-0Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/13V3 - Resistor settings show V2, not V32019-06-13T13:47:38ZErik van der BijV3 - Resistor settings show V2, not V3There are some resistors that should show which version of PCB is
used.
Unfortunately the settings on the V3 are the same as on the V2.
Not a problem as they are fully compatible.
Make sure new versions have the correct setting.EDA-02530-V4-0Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/14PTS: timing violation in DAC signal.2022-12-05T15:07:08ZErik van der BijPTS: timing violation in DAC signal.See [attached file](https://www.ohwr.org/project/svec/uploads/5f2da47ee102a92e58c5a17a3ee5f469/PTS_7Sv02.pdf)
According to the Fig. 2 shown in the AD5662 datasheet, it is clear that
chip uses the negative clock
edge to latch the data, with a setup/hold time given by t5 and t6.
The PTS test used for the SVEC/SPEC board changes DAC DIN signal at
exactly the falling SCLK
edge. Therefore, it violates the timing conditions indicated in the
datasheet (setup time=5ns and hold
time=4.5ns) as shown in Figure 1.
This produces that voltage values written from Python code are wrong and
do not correspond with the
real values presented at the DAC output (as measured with an
oscilloscope).
Problem not urgent as the PTS basically only has to check if every
solder connection is correctly done, even with the problem present, it
will detect if the DAC would not be correctly connected.
### Files
* [PTS_7Sv02.pdf](/uploads/5f2da47ee102a92e58c5a17a3ee5f469/PTS_7Sv02.pdf)https://ohwr.org/project/svec/issues/19V2 - Flash memory M25P128-VME6G obsolete2020-01-07T10:54:35ZErik van der BijV2 - Flash memory M25P128-VME6G obsoleteThe Flash memory NUMONYX (MICRON) M25P128-VME6G is obsolete.
The replacement part seems to be M25P128-VME6GB.
[Datasheet](http://download.siliconexpert.com/pdfs/2010/3/8/1/11/41/543/nmnyx_/manual/m25p128.pdf).
The difference is the process technology:
\- Blank = 130nm MLC
\- B = 65 nm SLC
- Verify the suggested replacement type.
- AC and DC characteristics are different between 130nm and 65nm
devices.
- Test on an actual board if needed.
- Update schematics with new symbol.
- Update production documents.https://ohwr.org/project/svec/issues/21V2 - Pullback on top and bottom layers is too small2019-06-13T13:47:39ZProjectsV2 - Pullback on top and bottom layers is too smallPullback on top and bottom layers (for ESD polygons) is 0.192mm and
should be at least 0.2mm
### Files
* [Screenshot-rdesktop_-_rdseda19.cern.ch-1.png](/uploads/d51211a3c99fa59cbb8511e857d525db/Screenshot-rdesktop_-_rdseda19.cern.ch-1.png)EDA-02530-V4-0Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/svec/issues/29V1 - Uneven track width2019-06-13T13:47:39ZProjectsV1 - Uneven track widthSome tracks for similar signals (e.g. VME signals) have uneven track
width.
### Files
* [SVEC_track_width.jpg](/uploads/43d56f67f8170fb23bdfe5f4ee683007/SVEC_track_width.jpg)EDA-02530-V4-0Tomasz WlostowskiTomasz Wlostowski