Programming languages used in this repository
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VHDL
46.18 %
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Verilog
25.69 %
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SystemVerilog
10.94 %
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C
9.33 %
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Stata
2.99 %
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HTML
2.17 %
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Python
1.08 %
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Lua
1.01 %
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Makefile
0.39 %
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Tcl
0.18 %
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Shell
0.05 %
Commit statistics for tgingold-testcard Jun 08 - Feb 08
- Total: 282 commits
- Average per day: 0.1 commits
- Authors: 10
Commits per day of month
Commits per weekday
Commits per day hour (UTC)