Programming languages used in this repository

  •   VHDL
    46.8 %
  •   Verilog
    26.01 %
  •   SystemVerilog
    11.08 %
  •   C
    8.3 %
  •   Stata
    3.03 %
  •   HTML
    2.2 %
  •   Python
    1.06 %
  •   Lua
    1.02 %
  •   Makefile
    0.28 %
  •   Tcl
    0.18 %
  •   Shell
    0.05 %

Commit statistics for d36a4c1469722afa996ad80bc83116fcb44a63ec Jun 08 - Aug 22

  • Total: 98 commits
  • Average per day: 0.0 commits
  • Authors: 4

Commits per day of month

Commits per weekday

Commits per day hour (UTC)