Commits · d8f4adcce0e160430f639fb52a625525f891d06a · Projects / Simple VME FMC Carrier SVEC · Open Hardware Repository

02 Aug, 2019 2 commits
- [hdl] move UCFs to syn/common restructure DDR constraints · d8f4adcc
  Dimitris Lampridis authored Aug 02, 2019
  
  d8f4adcc
- [hdl] relax DMTD phase constraint · 53203b3c
  Dimitris Lampridis authored Aug 02, 2019
  
  53203b3c
25 Jul, 2019 7 commits
- [hdl] fix front-panel GPIO locations, they were inverted · 416aea5d
  Dimitris Lampridis authored Jul 25, 2019
  
  416aea5d
- [hdl] rework cross-clock domain constraints · f5c8df30
  Dimitris Lampridis authored Jul 25, 2019
  
  f5c8df30
- [hdl] move DDR constraints to their dedicated UCF files · badab820
  Dimitris Lampridis authored Jul 25, 2019
  
  badab820
- [doc] add clk_20m_vcxo_i LOC constraints · 6cb80a43
  Dimitris Lampridis authored Jul 25, 2019
  
  6cb80a43
- [hdl] drive SPI outputs to zero when g_WITH_SPI is not set · 28935e4f
  Dimitris Lampridis authored Jul 25, 2019
  
  28935e4f
- testbench: drives ddr4. · d9e35137
  Tristan Gingold authored Jul 25, 2019
  
  d9e35137
- svec_template_wr: specify granularity of ddr4. · eed7920a
  Tristan Gingold authored Jul 25, 2019
  
  eed7920a
24 Jul, 2019 8 commits
- [hdl] add default values to DDR WB interfaces · 7e91ab32
  Dimitris Lampridis authored Jul 24, 2019
  
  7e91ab32
- [hdl] expose external WR 10MHz clock and PPS inputs · 5a28f2c8
  Dimitris Lampridis authored Jul 24, 2019
  
  5a28f2c8
- [hdl] expose WR aux clock interface · 0ea886c0
  Dimitris Lampridis authored Jul 24, 2019
  
  0ea886c0
- Add testbench for template. · 1ed0766d
  Tristan Gingold authored Jul 24, 2019
  
  1ed0766d
- svec template: use vme64x core in pipelined mode. · 06336586
  Tristan Gingold authored Jul 24, 2019
  
  06336586
- Regenerate svec_template_regs. · 1ee43aec
  Tristan Gingold authored Jul 24, 2019
  
  1ee43aec
- [hdl] add root Manifest · fe843b2b
  Dimitris Lampridis authored Jul 24, 2019
  
  fe843b2b
- [hdl] update submodules to new OHWR and point to latest stable commits · 566559f0
  Dimitris Lampridis authored Jul 24, 2019
  
  566559f0
23 Jul, 2019 1 commit
- svec template: add ddr registers. · bbe9114e
  Tristan Gingold authored Jul 23, 2019
  
  bbe9114e
22 Jul, 2019 1 commit
- add golden_wr · a8d09a80
  Tristan Gingold authored Jul 22, 2019
  
  a8d09a80
19 Jul, 2019 1 commit
- Update svec template. · 7381dcab
  Tristan Gingold authored Jul 19, 2019
  
  7381dcab
18 Jul, 2019 1 commit
- Add initial version of svec template. · 7c4136db
  Tristan Gingold authored Jul 18, 2019
  
  7c4136db
18 Sep, 2017 3 commits
- remove unused project files · 481562e0
  Dimitris Lampridis authored Sep 13, 2017
  
  481562e0
- golden: remove Xilinx ISE project file and introduce hdlmake Manifest.py for synthesis · 8e2745f6
  Dimitris Lampridis authored Sep 13, 2017
```
sfpga_bootloader: remove Xilinx ISE project file and update hdlmake Manifest.py for synthesis

Solves #1642
```
  8e2745f6
- golden: add missing timing constraint for 20MHz VCXO clock input. Solves #1641. · cf49b099
  Dimitris Lampridis authored Sep 13, 2017
  
  cf49b099
19 Mar, 2015 4 commits
- vme-flasher: removed CERN specific makefile options · b3454979
  Tomasz Wlostowski authored Mar 19, 2015
  
  b3454979
- software: removed obsolete sveclib · f6c7fa2c
  Tomasz Wlostowski authored Mar 19, 2015
  
  f6c7fa2c
- vme-flasher: added loading bitstream to AFPGA mode without programming the flash · b72b6669
  Tomasz Wlostowski authored Mar 19, 2015
  
  b72b6669
- svec-flasher: added support for direct FPGA booting · 7a6e1838
  Tomasz Wlostowski authored Mar 19, 2015
  
  7a6e1838
26 Nov, 2014 1 commit
- Updated documentation date · f2a7a4e0
  Tomasz Wlostowski authored Nov 26, 2014
  
  f2a7a4e0
15 Aug, 2014 2 commits
- svec-flasher: added update over VME option · 2368263a
  Tomasz Wlostowski authored Aug 15, 2014
  
  2368263a
- sfpga_bootloader: provide SPI flash to AFPGA when the bootloader is done · f2768ddc
  Tomasz Wlostowski authored Aug 15, 2014
  
  f2768ddc
02 Apr, 2014 2 commits
- hdl/golden: updated manifest & ISE project · b2d7a10f
  Tomasz Wlostowski authored Apr 02, 2014
  
  b2d7a10f
- doc/gateware-manual: removed vebatim links to bitstreams, replaced with the Release wiki page · 1bf411bd
  Tomasz Wlostowski authored Apr 02, 2014
  
  1bf411bd
06 Mar, 2014 1 commit
- ip_cores/vme64x-core: apply 0.5 MB A24 fix · 0eb7c8e3
  Tomasz Wlostowski authored Mar 06, 2014
  
  0eb7c8e3
07 Feb, 2014 4 commits
- hdl/top/golden: updated synthesis descriptor · 91cf2d3d
  Tomasz Wlostowski authored Feb 07, 2014
  
  91cf2d3d
- hdl/top/sfpga_bootloader: pulse PLL_CE pin on startup to avoid potential… · b4291a52
  Tomasz Wlostowski authored Feb 07, 2014
```
hdl/top/sfpga_bootloader: pulse PLL_CE pin on startup to avoid potential CDCM61004 PLL locking issues
```
  b4291a52
- hdl/rtl/bootloader: re-genrated WB slave using latest wbgen2 (with FIFO CSR.CLEAR bit fix) · 2e540239
  Tomasz Wlostowski authored Feb 07, 2014
  
  2e540239
- doc: updated referneces to gateware files · da081f46
  Tomasz Wlostowski authored Feb 07, 2014
  
  da081f46
04 Feb, 2014 2 commits
- hdl/rtl/golden: uploaded missing golden core files · 41bb7c77
  Tomasz Wlostowski authored Feb 04, 2014
  
  41bb7c77
- top: updated ISE projects to use latest versions of submodules (general-cores &… · 49885ae7
  Tomasz Wlostowski authored Feb 04, 2014
```
top: updated ISE projects to use latest versions of submodules (general-cores & vme64x-core). Added synthesis descriptor in the golden bitstream.
```
  49885ae7