Commits · 54618b729a0112964f19b9bd6222f5aeb4b22865 · Projects / Simple VME FMC Carrier SVEC · Open Hardware Repository

02 Oct, 2020 7 commits
- svec7: updated constraint files with pin assignment · 54618b72
  Tomasz Wlostowski authored Oct 02, 2020
  
  54618b72
- svec7: SFPGA top level test with final FPGA Pinout · add3785a
  Tomasz Wlostowski authored Oct 02, 2020
  
  add3785a
- svec7: dummy synthesizable top level with GTXes, DDR controller and WR · d02d1f4a
  Tomasz Wlostowski authored Oct 02, 2020
  
  d02d1f4a
- svec7_base_wr: apply final PCB FPGA pinout · be55889a
  Tomasz Wlostowski authored Oct 02, 2020
  
  be55889a
- scripts: xilinx pin assigner script [wip] · dfd58450
  Tomasz Wlostowski authored Oct 02, 2020
  
  dfd58450
- platform: re-genrated MIG for final pin assignment · abea73b8
  Tomasz Wlostowski authored Oct 02, 2020
  
  abea73b8
- ip_cores: updated submodules · 24f4dcea
  Tomasz Wlostowski authored Oct 02, 2020
  
  24f4dcea
19 Dec, 2019 1 commit
- wip · 43fa5537
  Tomasz Wlostowski authored Dec 19, 2019
  
  43fa5537
12 Dec, 2019 1 commit
- syn: svec7 XDC & synthesis files · bd991588
  Tomasz Wlostowski authored Dec 12, 2019
  
  bd991588
11 Dec, 2019 2 commits
- svec7: test top level with all pins placed, passes P&R · 39d8e652
  Tomasz Wlostowski authored Dec 11, 2019
  
  39d8e652
- updated submoudles · 94c5a4ca
  Tomasz Wlostowski authored Dec 11, 2019
  
  94c5a4ca
02 Dec, 2019 1 commit
- svec7: proof of concept VME-serial bridge to save on FPGA pins · 37d6449f
  Tomasz Wlostowski authored Dec 02, 2019
  
  37d6449f
27 Nov, 2019 1 commit
- bridge testing · 29b98259
  Tomasz Wlostowski authored Nov 27, 2019
  
  29b98259
18 Oct, 2019 1 commit
- svec7: test project · 90348ce2
  Tomasz Wlostowski authored Oct 18, 2019
  
  90348ce2
15 Oct, 2019 1 commit
- svec_base_wr: added DDMTD clock output · 41415b81
  Tomasz Wlostowski authored Oct 15, 2019
  
  41415b81
25 Sep, 2019 1 commit
- sw:drv: fix I2C filter function · cf6b2894
  Federico Vaga authored Sep 25, 2019
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  cf6b2894
24 Sep, 2019 3 commits
- sw:drv: follow HDL renaming template -> base · 84ff1837
  Federico Vaga authored Sep 24, 2019
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  84ff1837
- Merge remote-tracking branch 'origin/proposed_master' into develop · dcea0685
  Federico Vaga authored Sep 24, 2019
  
  dcea0685
- Update golden after renaming. · 4b432b68
  Tristan Gingold authored Sep 24, 2019
  
  4b432b68
23 Sep, 2019 1 commit
- Rename template -> base · 46bd7e78
  Tristan Gingold authored Sep 23, 2019
  
  46bd7e78
11 Sep, 2019 3 commits
- sw:drv: validate input · 42aca0a7
  Federico Vaga authored Sep 11, 2019
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  42aca0a7
- sw:drv: bugfix use correct funciton number · a8abe33e
  Federico Vaga authored Sep 11, 2019
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  a8abe33e
- sw:drv: fix app_id build · e356c034
  Federico Vaga authored Sep 11, 2019
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  e356c034
23 Aug, 2019 1 commit
- sw:drv: add debug message when programming FPGA · 44fd8dba
  Federico Vaga authored Aug 23, 2019
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  44fd8dba
22 Aug, 2019 11 commits
- Merge remote-tracking branch 'origin/proposed_master' into develop · 1632a555
  Federico Vaga authored Aug 22, 2019
  
  1632a555
- svec golden wr: fix port names, connexions... Tested ok. · 3da89c5c
  Tristan Gingold authored Aug 22, 2019
  
  3da89c5c
- svec template: fix interrupt wiring. · bcf5473e
  Tristan Gingold authored Aug 22, 2019
  
  bcf5473e
- sw:drv: fix build info endianess · 4df4d362
  Federico Vaga authored Aug 22, 2019
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  4df4d362
- sw:drv: generate FPGA header file from cheby · e8ea30b3
  Federico Vaga authored Aug 22, 2019
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  e8ea30b3
- sw:drv: ignore files · 324246cd
  Federico Vaga authored Aug 22, 2019
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  324246cd
- Merge branch 'proposed_master' into develop · 58314b58
  Federico Vaga authored Aug 22, 2019
  
  58314b58
- sw:drv: re-apply lost changes in sw|hdl merge · 7035a37a
  Federico Vaga authored Aug 22, 2019
```
something was defentivelly wrong during the merge and I missed it.
This patch re-apply the good code
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  7035a37a
- sw: move tools to tools/ directory · d36a4c14
  Federico Vaga authored Aug 22, 2019
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  d36a4c14
- sw: move to software directory · 14b5cd97
  Federico Vaga authored Aug 22, 2019
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  14b5cd97
- Merge remote-tracking branch 'sw/master' · d1acc791
  Federico Vaga authored Aug 22, 2019
  
  d1acc791
02 Aug, 2019 2 commits
- [hdl] move UCFs to syn/common restructure DDR constraints · d8f4adcc
  Dimitris Lampridis authored Aug 02, 2019
  
  d8f4adcc
- [hdl] relax DMTD phase constraint · 53203b3c
  Dimitris Lampridis authored Aug 02, 2019
  
  53203b3c
25 Jul, 2019 3 commits
- [hdl] fix front-panel GPIO locations, they were inverted · 416aea5d
  Dimitris Lampridis authored Jul 25, 2019
  
  416aea5d
- [hdl] rework cross-clock domain constraints · f5c8df30
  Dimitris Lampridis authored Jul 25, 2019
  
  f5c8df30
- [hdl] move DDR constraints to their dedicated UCF files · badab820
  Dimitris Lampridis authored Jul 25, 2019
  
  badab820