Commits · 41415b8141e5466248e55eadd30ba4a68e4b3e21 · Projects / Simple VME FMC Carrier SVEC · Open Hardware Repository

15 Oct, 2019 1 commit
- svec_base_wr: added DDMTD clock output · 41415b81
  Tomasz Wlostowski authored Oct 15, 2019
  
  41415b81
25 Sep, 2019 1 commit
- sw:drv: fix I2C filter function · cf6b2894
  Federico Vaga authored Sep 25, 2019
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  cf6b2894
24 Sep, 2019 3 commits
- sw:drv: follow HDL renaming template -> base · 84ff1837
  Federico Vaga authored Sep 24, 2019
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  84ff1837
- Merge remote-tracking branch 'origin/proposed_master' into develop · dcea0685
  Federico Vaga authored Sep 24, 2019
  
  dcea0685
- Update golden after renaming. · 4b432b68
  Tristan Gingold authored Sep 24, 2019
  
  4b432b68
23 Sep, 2019 1 commit
- Rename template -> base · 46bd7e78
  Tristan Gingold authored Sep 23, 2019
  
  46bd7e78
11 Sep, 2019 3 commits
- sw:drv: validate input · 42aca0a7
  Federico Vaga authored Sep 11, 2019
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  42aca0a7
- sw:drv: bugfix use correct funciton number · a8abe33e
  Federico Vaga authored Sep 11, 2019
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  a8abe33e
- sw:drv: fix app_id build · e356c034
  Federico Vaga authored Sep 11, 2019
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  e356c034
23 Aug, 2019 1 commit
- sw:drv: add debug message when programming FPGA · 44fd8dba
  Federico Vaga authored Aug 23, 2019
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  44fd8dba
22 Aug, 2019 11 commits
- Merge remote-tracking branch 'origin/proposed_master' into develop · 1632a555
  Federico Vaga authored Aug 22, 2019
  
  1632a555
- svec golden wr: fix port names, connexions... Tested ok. · 3da89c5c
  Tristan Gingold authored Aug 22, 2019
  
  3da89c5c
- svec template: fix interrupt wiring. · bcf5473e
  Tristan Gingold authored Aug 22, 2019
  
  bcf5473e
- sw:drv: fix build info endianess · 4df4d362
  Federico Vaga authored Aug 22, 2019
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  4df4d362
- sw:drv: generate FPGA header file from cheby · e8ea30b3
  Federico Vaga authored Aug 22, 2019
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  e8ea30b3
- sw:drv: ignore files · 324246cd
  Federico Vaga authored Aug 22, 2019
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  324246cd
- Merge branch 'proposed_master' into develop · 58314b58
  Federico Vaga authored Aug 22, 2019
  
  58314b58
- sw:drv: re-apply lost changes in sw|hdl merge · 7035a37a
  Federico Vaga authored Aug 22, 2019
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something was defentivelly wrong during the merge and I missed it.
This patch re-apply the good code
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  7035a37a
- sw: move tools to tools/ directory · d36a4c14
  Federico Vaga authored Aug 22, 2019
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  d36a4c14
- sw: move to software directory · 14b5cd97
  Federico Vaga authored Aug 22, 2019
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  14b5cd97
- Merge remote-tracking branch 'sw/master' · d1acc791
  Federico Vaga authored Aug 22, 2019
  
  d1acc791
02 Aug, 2019 2 commits
- [hdl] move UCFs to syn/common restructure DDR constraints · d8f4adcc
  Dimitris Lampridis authored Aug 02, 2019
  
  d8f4adcc
- [hdl] relax DMTD phase constraint · 53203b3c
  Dimitris Lampridis authored Aug 02, 2019
  
  53203b3c
25 Jul, 2019 7 commits
- [hdl] fix front-panel GPIO locations, they were inverted · 416aea5d
  Dimitris Lampridis authored Jul 25, 2019
  
  416aea5d
- [hdl] rework cross-clock domain constraints · f5c8df30
  Dimitris Lampridis authored Jul 25, 2019
  
  f5c8df30
- [hdl] move DDR constraints to their dedicated UCF files · badab820
  Dimitris Lampridis authored Jul 25, 2019
  
  badab820
- [doc] add clk_20m_vcxo_i LOC constraints · 6cb80a43
  Dimitris Lampridis authored Jul 25, 2019
  
  6cb80a43
- [hdl] drive SPI outputs to zero when g_WITH_SPI is not set · 28935e4f
  Dimitris Lampridis authored Jul 25, 2019
  
  28935e4f
- testbench: drives ddr4. · d9e35137
  Tristan Gingold authored Jul 25, 2019
  
  d9e35137
- svec_template_wr: specify granularity of ddr4. · eed7920a
  Tristan Gingold authored Jul 25, 2019
  
  eed7920a
24 Jul, 2019 8 commits
- [hdl] add default values to DDR WB interfaces · 7e91ab32
  Dimitris Lampridis authored Jul 24, 2019
  
  7e91ab32
- [hdl] expose external WR 10MHz clock and PPS inputs · 5a28f2c8
  Dimitris Lampridis authored Jul 24, 2019
  
  5a28f2c8
- [hdl] expose WR aux clock interface · 0ea886c0
  Dimitris Lampridis authored Jul 24, 2019
  
  0ea886c0
- Add testbench for template. · 1ed0766d
  Tristan Gingold authored Jul 24, 2019
  
  1ed0766d
- svec template: use vme64x core in pipelined mode. · 06336586
  Tristan Gingold authored Jul 24, 2019
  
  06336586
- Regenerate svec_template_regs. · 1ee43aec
  Tristan Gingold authored Jul 24, 2019
  
  1ee43aec
- [hdl] add root Manifest · fe843b2b
  Dimitris Lampridis authored Jul 24, 2019
  
  fe843b2b
- [hdl] update submodules to new OHWR and point to latest stable commits · 566559f0
  Dimitris Lampridis authored Jul 24, 2019
  
  566559f0
23 Jul, 2019 1 commit
- svec template: add ddr registers. · bbe9114e
  Tristan Gingold authored Jul 23, 2019
  
  bbe9114e
22 Jul, 2019 1 commit
- add golden_wr · a8d09a80
  Tristan Gingold authored Jul 22, 2019
  
  a8d09a80