golden_wr: adjust after renaming of template to base.

f9f8b764 · Tristan Gingold · 6a88647a · f9f8b764 · f9f8b764 · f9f8b764
Commit f9f8b764 authored Apr 09, 2020 by Tristan Gingold
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Showing with 4 additions and 2 deletions

Manifest.py hdl/syn/golden_wr/Manifest.py +1 -1

svec_golden.vhd hdl/top/golden/svec_golden.vhd +1 -0

svec_golden_wr.vhd hdl/top/golden_wr/svec_golden_wr.vhd +2 -1

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--- a/hdl/syn/golden_wr/Manifest.py
+++ b/hdl/syn/golden_wr/Manifest.py
@@ -16,7 +16,7 @@ syn_top = "svec_golden_wr"
 board = "svec"
 ctrls = ["bank4_64b_32b"]

-svec_template_ucf = ['ddr4', 'wr', 'gpio', 'led']
+svec_base_ucf = ['ddr4', 'wr', 'gpio', 'led']

 files = [ "buildinfo_pkg.vhd" ]


--- a/hdl/top/golden/svec_golden.vhd
+++ b/hdl/top/golden/svec_golden.vhd
@@ -150,6 +150,7 @@ architecture top of svec_golden is
 begin
  inst_svec_base: entity work.svec_base_wr
    generic map (
+      g_DECODE_AM => False,
      g_with_vic => True,
      g_with_onewire => True,
      g_with_spi => True,

--- a/hdl/top/golden_wr/svec_golden_wr.vhd
+++ b/hdl/top/golden_wr/svec_golden_wr.vhd
@@ -217,8 +217,9 @@ architecture top of svec_golden_wr is

  signal pps_p : std_logic;
 begin
-  inst_svec_template: entity work.svec_template_wr
+  inst_svec_base: entity work.svec_base_wr
    generic map (
+      g_DECODE_AM => False,
      g_with_vic => True,
      g_with_onewire => False,
      g_with_spi => True,