Commit f2768ddc authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

sfpga_bootloader: provide SPI flash to AFPGA when the bootloader is done

parent b2d7a10f
......@@ -35,15 +35,15 @@
@setchapternewpage off
@set update-month February 2014
@set update-month August 2014
@include git_revision.in
@finalout
@titlepage
@title Standard SVEC Gateware
@subtitle Programmer and User manual (Git revision: @code{@value{git-revision}})
@author CERN BE-CO-HT / Tomasz Włostowski, @value{update-month}
@subtitle Programmer and User manual (Git revision: @code{@value{git-revision}}, @value{update-month})
@author CERN BE-CO-HT / Tomasz Włostowski
@end titlepage
@headings single
......@@ -78,10 +78,11 @@ The System FPGA bootloader allows to boot the Application FPGA from the VME bus
@section Bootloader versions
There are two versions of the bootloader in use:
There are three versions of the bootloader in use:
@itemize
@item The new one (a.k.a. version 2) which supports everything described in this manual.
@item The old one (version 1) which only allows booting the Application FPGA via VME (no flash support). This version of the bootloader has been programmed in older SVEC cards. If the VME flasher (@code{svec-flasher}) tool is unable to detect the flash memory, you're likely running the old bootloader.
@item @b{Version 1} which only allows booting the Application FPGA via VME (no flash support). This version of the bootloader has been programmed in older SVEC cards. If the VME flasher (@code{svec-flasher}) tool is unable to detect the flash memory, you're likely running the old bootloader.
@item @b{Version 2} which supports everything described in this manual except for providing SPI flash access to the AFPGA.
@item @b{Version 3} which supports everything described in this manual, including accessing the SPI flash from AFPGA.
@end itemize
The new version is software-compatible with the old one, there is no need to update any drivers. The register description applies to both versions, except that for the version 1, the Flash Access Register (@code{FAR}) is not functional.
......@@ -130,6 +131,7 @@ The flash memory of the SVEC contains 16 Megabytes of data, that is 65536 pages
@itemize
@item @code{0}: Raw bitstream for the System FPGA (up to 1 MB).
@item @code{0x100000}: Raw bitstream for the Application FPGA (up to 5 MB).
@item @code{0x601000 - 0xffffff}: User-defined area, foreseen for AFPGA data storage.
@end itemize
An example script for building the default flash filesystem (containg the bootloader and golden bitstreams) is located in the @code{software/sdb-flash} subdirectory in the SVEC project's repository(@pxref{repo_link,,2}). Presence of the SDB descriptor table at @code{0x600000} is checked by the bootloader to prevent booting up from a corrupted or unprogrammed flash.
......@@ -258,6 +260,23 @@ Preparation of the flash image described above requires some (currently) Linux-o
@item Store the image in Intel HEX (@code{.mcs} extension format) and flash using Xilinx Impact.
@end itemize
@section Accessing the SPI Flash from the Application FPGA
The Version 3 of the bootloader allows the Application FPGA to access the SPI interface of the Flash memory. Once the boot process is done, the System FPGA routes the following AFPGA pins
directly to the Flash memory's SPI interface (Xilinx UCF file syntax):
@example
NET "flash_sck_o" LOC=AG26;
NET "flash_mosi_o" LOC=AH26;
NET "flash_cs_n_o" LOC=AG27;
NET "flash_miso_i" LOC=AH27;
NET "flash_sck_o" IOSTANDARD = "LVCMOS33";
NET "flash_mosi_o" IOSTANDARD = "LVCMOS33";
NET "flash_cs_n_o" IOSTANDARD = "LVCMOS33";
NET "flash_miso_i" IOSTANDARD = "LVCMOS33";
@end example
@page
@chapter References
@enumerate
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : svec_xloader_wb.vhd
-- Author : auto-generated by wbgen2 from svec_xloader_wb.wb
-- Created : Fri Feb 7 11:31:10 2014
-- Created : Mon Aug 11 10:59:42 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE svec_xloader_wb.wb
......@@ -131,7 +131,7 @@ begin
rddata_reg(5) <= '0';
rddata_reg(6) <= '0';
rddata_reg(13 downto 8) <= sxldr_csr_clkdiv_int;
rddata_reg(21 downto 14) <= "00000010";
rddata_reg(21 downto 14) <= "00000011";
rddata_reg(7) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
......
......@@ -125,7 +125,7 @@ peripheral {
prefix = "VERSION";
type = CONSTANT;
size = 8;
value = 2;
value = 3;
}
};
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : sxldr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from svec_xloader_wb.wb
-- Created : Fri Feb 7 11:31:10 2014
-- Created : Mon Aug 11 10:59:42 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE svec_xloader_wb.wb
......
......@@ -9,7 +9,7 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
......@@ -161,6 +161,7 @@
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
......@@ -716,6 +717,6 @@
<bindings/>
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
</project>
......@@ -250,6 +250,17 @@ NET "lclk_n_i" IOSTANDARD="LVCMOS33";
NET "pll_ce_o" IOSTANDARD="LVCMOS33";
NET "pll_ce_o" LOC=G14;
NET "afpga_flash_sck_i" LOC=G16;
NET "afpga_flash_mosi_i" LOC=H15;
NET "afpga_flash_cs_n_i" LOC=H16;
NET "afpga_flash_miso_o" LOC=J14;
NET "afpga_flash_sck_i" IOSTANDARD=LVCMOS33;
NET "afpga_flash_mosi_i" IOSTANDARD=LVCMOS33;
NET "afpga_flash_cs_n_i" IOSTANDARD=LVCMOS33;
NET "afpga_flash_miso_o" IOSTANDARD=LVCMOS33;
#Created by Constraints Editor (xc6slx9-ftg256-2) - 2014/01/15
NET "lclk_n_i" TNM_NET = lclk_n_i;
TIMESPEC TS_lclk_n_i = PERIOD "lclk_n_i" 20 MHz HIGH 50%;
......@@ -104,6 +104,15 @@ entity svec_sfpga_top is
debugled_n_o : out std_logic_vector(2 downto 1);
-------------------------------------------------------------------------
-- Slave SPI interface allowing the Application FPGA to access the SPI flash
-------------------------------------------------------------------------
afpga_flash_sck_i : in std_logic;
afpga_flash_mosi_i : in std_logic;
afpga_flash_cs_n_i : in std_logic;
afpga_flash_miso_o : out std_logic;
-- Onboard PLL enable signal. Must be one for the clock system to work.
pll_ce_o : out std_logic
......@@ -227,6 +236,9 @@ architecture rtl of svec_sfpga_top is
signal pll_reset_count : unsigned(15 downto 0);
signal spi_cs_n_int, spi_mosi_int, spi_sclk_int : std_logic;
signal pass_flash: std_logic;
begin
-- PLL for producing 83.3 MHz system clock (clk_sys) from a 20 MHz reference.
......@@ -362,9 +374,9 @@ begin
boot_trig_p1_o => boot_trig_p1,
boot_exit_p1_o => boot_exit_p1,
boot_en_i => boot_en,
spi_cs_n_o => spi_cs_n_o,
spi_sclk_o => spi_sclk_o,
spi_mosi_o => spi_mosi_o,
spi_cs_n_o => spi_cs_n_int,
spi_sclk_o => spi_sclk_int,
spi_mosi_o => spi_mosi_int,
spi_miso_i => spi_miso_i);
-- produces a longer pulse on PROGRAM_B pin of the Application FPGA when
......@@ -425,6 +437,13 @@ begin
end if;
end process;
-- multiplex flash access between the AFPGA and SFPGA bootloader (if the
-- AFPGA is programmed, it's wired to the SPI flash).
spi_cs_n_o <= spi_cs_n_int when boot_done_i = '0' else afpga_flash_cs_n_i;
spi_sclk_o <= spi_sclk_int when boot_done_i = '0' else afpga_flash_sck_i;
spi_mosi_o <= spi_mosi_int when boot_done_i = '0' else afpga_flash_mosi_i;
afpga_flash_miso_o <= spi_miso_i;
-- When the VME bootloader is not active, do NOT drive any outputs and sit quiet.
passive <= not boot_en;
......
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