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Simple VME FMC Carrier SVEC
Commit eaa566b7 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: delete unused top-level HDL modules

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hdl/top/bicolor_led_test/Manifest.py deleted 100644 → 0
View file @ 454b1dbb
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0
files = ["bicolor_led_ctrl_pkg.vhd",
"bicolor_led_ctrl.vhd",
"wb_addr_decoder.vhd",
"svec_afpga_top.vhd",
"csr.vhd",
"svec_v0_afpga.ucf"]
fetchto = "ip_cores"
modules = {
"git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git" ],
"svn" : [ "http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl",
"http://svn.ohwr.org/ddr3-sp6-core/trunk/hdl" ]
}
hdl/top/bicolor_led_test/bicolor_led_ctrl.vhd deleted 100644 → 0
View file @ 454b1dbb
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Bi-color LED controller. It controls a matrix of bi-color LED.
-- The FPGA ouputs for the columns (C) are connected to buffers
-- and serial resistances and then to the LEDs. The FPGA outputs
-- for lines (L) are connected to tri-state buffers and the to
-- the LEDs. The FPGA outputs for lines output enable (L_OEN) are
-- connected to the output enable of the tri-state buffers.
--
-- Example with three lines and two columns:
--
-- |<refresh period>|
--
-- L1/L2/L3 __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__
--
-- L1_OEN -----|___________|-----|___________|-----|___________|-----|___________|--
--
-- L2_OEN _____|-----|___________|-----|___________|-----|___________|-----|________
--
-- L3_OEN ___________|-----|___________|-----|___________|-----|___________|-----|__
--
-- Cn __|--|__|--|__|--|_________________|-----------------|--|__|--|__|--|__|--
--
-- LED Ln/Cn OFF | color_1 | color_2 | both_colors |
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.bicolor_led_ctrl_pkg.all;
entity bicolor_led_ctrl is
generic(
g_NB_COLUMN : natural := 4;
g_NB_LINE : natural := 2;
g_CLK_FREQ : natural := 125000000; -- in Hz
g_REFRESH_RATE : natural := 250 -- in Hz
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
line_o : out std_logic_vector(g_NB_LINE - 1 downto 0);
line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
);
end bicolor_led_ctrl;
architecture rtl of bicolor_led_ctrl is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_REFRESH_CNT_INIT : natural := natural(g_CLK_FREQ/(2 * g_NB_LINE * g_REFRESH_RATE)) - 1;
constant c_REFRESH_CNT_NB_BITS : natural := log2_ceil(c_REFRESH_CNT_INIT);
constant c_LINE_OEN_CNT_NB_BITS : natural := log2_ceil(g_NB_LINE);
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal refresh_rate_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
signal refresh_rate : std_logic;
signal line_ctrl : std_logic;
signal intensity_ctrl_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
signal intensity_ctrl : std_logic;
signal line_oen_cnt : unsigned(c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
signal line_oen : std_logic_vector(2**c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
signal led_state : std_logic_vector((g_NB_LINE * g_NB_COLUMN) -1 downto 0);
begin
------------------------------------------------------------------------------
-- Refresh rate counter
------------------------------------------------------------------------------
p_refresh_rate_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
refresh_rate_cnt <= (others => '0');
refresh_rate <= '0';
elsif refresh_rate_cnt = 0 then
refresh_rate_cnt <= to_unsigned(c_REFRESH_CNT_INIT, c_REFRESH_CNT_NB_BITS);
refresh_rate <= '1';
else
refresh_rate_cnt <= refresh_rate_cnt - 1;
refresh_rate <= '0';
end if;
end if;
end process p_refresh_rate_cnt;
------------------------------------------------------------------------------
-- Intensity control
------------------------------------------------------------------------------
p_intensity_ctrl_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
intensity_ctrl_cnt <= (others => '0');
elsif refresh_rate = '1' then
intensity_ctrl_cnt <= to_unsigned(natural(c_REFRESH_CNT_INIT/100) * to_integer(unsigned(led_intensity_i)), c_REFRESH_CNT_NB_BITS);
else
intensity_ctrl_cnt <= intensity_ctrl_cnt - 1;
end if;
end if;
end process p_intensity_ctrl_cnt;
p_intensity_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
intensity_ctrl <= '0';
elsif refresh_rate = '1' then
intensity_ctrl <= '1';
elsif intensity_ctrl_cnt = 0 then
intensity_ctrl <= '0';
end if;
end if;
end process p_intensity_ctrl;
------------------------------------------------------------------------------
-- Lines ouput
------------------------------------------------------------------------------
p_line_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
line_ctrl <= '0';
elsif refresh_rate = '1' then
line_ctrl <= not(line_ctrl);
end if;
end if;
end process p_line_ctrl;
f_line_o : for I in 0 to g_NB_LINE - 1 generate
line_o(I) <= line_ctrl and intensity_ctrl;
end generate f_line_o;
------------------------------------------------------------------------------
-- Lines output enable
------------------------------------------------------------------------------
p_line_oen_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
line_oen_cnt <= (others => '0');
elsif line_ctrl = '1' and refresh_rate = '1' then
if line_oen_cnt = 0 then
line_oen_cnt <= to_unsigned(g_NB_LINE - 1, c_LINE_OEN_CNT_NB_BITS);
else
line_oen_cnt <= line_oen_cnt - 1;
end if;
end if;
end if;
end process p_line_oen_cnt;
p_line_oen_decode : process(line_oen_cnt)
variable v_onehot : std_logic_vector((2**line_oen_cnt'length)-1 downto 0);
variable v_index : integer range 0 to (2**line_oen_cnt'length)-1;
begin
v_onehot := (others => '0');
v_index := 0;
for i in line_oen_cnt'range loop
if (line_oen_cnt(i) = '1') then
v_index := 2*v_index+1;
else
v_index := 2*v_index;
end if;
end loop;
v_onehot(v_index) := '1';
line_oen <= v_onehot;
end process p_line_oen_decode;
line_oen_o <= line_oen(line_oen_o'left downto 0);
------------------------------------------------------------------------------
-- Columns output
------------------------------------------------------------------------------
f_led_state : for I in 0 to (g_NB_COLUMN * g_NB_LINE) - 1 generate
led_state(I) <= '0' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED else
'1' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_GREEN else
(line_ctrl and intensity_ctrl) when led_state_i(2 * I + 1 downto 2 * I) = c_LED_OFF else
not(line_ctrl and intensity_ctrl) when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED_GREEN;
end generate f_led_state;
f_column_o : for C in 0 to g_NB_COLUMN - 1 generate
column_o(C) <= led_state(g_NB_COLUMN * to_integer(line_oen_cnt) + C);
end generate f_column_o;
end rtl;
hdl/top/bicolor_led_test/bicolor_led_ctrl_pkg.vhd deleted 100644 → 0
View file @ 454b1dbb
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller package
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl_pkg
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Package for Bi-color LED controller.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package bicolor_led_ctrl_pkg is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_LED_RED : std_logic_vector(1 downto 0) := "10";
constant c_LED_GREEN : std_logic_vector(1 downto 0) := "01";
constant c_LED_RED_GREEN : std_logic_vector(1 downto 0) := "11";
constant c_LED_OFF : std_logic_vector(1 downto 0) := "00";
------------------------------------------------------------------------------
-- Functions declaration
------------------------------------------------------------------------------
function log2_ceil(N : natural) return positive;
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component bicolor_led_ctrl
generic(
g_NB_COLUMN : natural := 4;
g_NB_LINE : natural := 2;
g_CLK_FREQ : natural := 125000000; -- in Hz
g_REFRESH_RATE : natural := 250 -- in Hz
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
line_o : out std_logic_vector(g_NB_LINE - 1 downto 0);
line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
);
end component;
end bicolor_led_ctrl_pkg;
package body bicolor_led_ctrl_pkg is
------------------------------------------------------------------------------
-- Function : Returns log of 2 of a natural number
------------------------------------------------------------------------------
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
end bicolor_led_ctrl_pkg;
hdl/top/bicolor_led_test/sim/bicolor_led.do deleted 100644 → 0
View file @ 454b1dbb
vsim -novopt -t 1ps bicolor_led_ctrl_tb
log -r /*
do wave.do
view wave
view transcript
run 100 ms
hdl/top/bicolor_led_test/sim/bicolor_led_ctrl_tb.vhd deleted 100644 → 0
View file @ 454b1dbb
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller testbench
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl_tb
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 12-07-2012
--
-- version: 1.0
--
-- description: Bi-color LED controller testbench.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.bicolor_led_ctrl_pkg.all;
entity bicolor_led_ctrl_tb is
end bicolor_led_ctrl_tb;
architecture tb of bicolor_led_ctrl_tb is
------------------------------------------------------------------------------
-- Types declaration
------------------------------------------------------------------------------
type t_led_color is (OFF, RED, GREEN, UNDEF);
type t_led_color_array is array (0 to 7) of t_led_color;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_NB_LINE : natural := 3;
constant c_NB_COLUMN : natural := 4;
constant c_CLK_FREQ : natural := 125000000; -- in Hz
constant c_REFRESH_RATE : natural := 250; -- in Hz
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal rst_n_i : std_logic := '1';
signal clk_i : std_logic := '0';
signal led_intensity_i : std_logic_vector(6 downto 0) := (others => '0');
signal led_state_i : std_logic_vector((c_NB_LINE * c_NB_COLUMN * 2) - 1 downto 0) := (others => '0');
signal column_o : std_logic_vector(c_NB_COLUMN - 1 downto 0);
signal line_o : std_logic_vector(c_NB_LINE - 1 downto 0);
signal line_oen_o : std_logic_vector(c_NB_LINE - 1 downto 0);
signal led_color : t_led_color_array;
begin
-- Instantiate the Unit Under Test (UUT)
uut : bicolor_led_ctrl
generic map (
g_NB_COLUMN => c_NB_COLUMN,
g_NB_LINE => c_NB_LINE,
g_CLK_FREQ => c_CLK_FREQ,
g_REFRESH_RATE => c_REFRESH_RATE
)
port map(
rst_n_i => rst_n_i,
clk_i => clk_i,
led_intensity_i => led_intensity_i,
led_state_i => led_state_i,
column_o => column_o,
line_o => line_o,
line_oen_o => line_oen_o
);
-- Clock process definitions
clk_i_process : process
begin
clk_i <= '0';
wait for 4 ns;
clk_i <= '1';
wait for 4 ns;
end process;
-- check color
p_led_color_check: process
begin
wait until (line_oen_o'event or line_o'event or column_o'event);
if (line_oen_o(0) = '0' or (line_oen_o(0) = '1' and line_o(0) = column_o(0))) then
led_color(0) <= OFF;
elsif (line_oen_o(0) = '1' and line_o(0) = '1' and column_o(0) = '0') then
led_color(0) <= RED;
elsif (line_oen_o(0) = '1' and line_o(0) = '0' and column_o(0) = '1') then
led_color(0) <= GREEN;
else
led_color(0) <= UNDEF;
end if;
if (line_oen_o(0) = '0' or (line_oen_o(0) = '1' and line_o(0) = column_o(1))) then
led_color(1) <= OFF;
elsif (line_oen_o(0) = '1' and line_o(0) = '1' and column_o(1) = '0') then
led_color(1) <= RED;
elsif (line_oen_o(0) = '1' and line_o(0) = '0' and column_o(1) = '1') then
led_color(1) <= GREEN;
else
led_color(1) <= UNDEF;
end if;
if (line_oen_o(0) = '0' or (line_oen_o(0) = '1' and line_o(0) = column_o(2))) then
led_color(2) <= OFF;
elsif (line_oen_o(0) = '1' and line_o(0) = '1' and column_o(2) = '0') then
led_color(2) <= RED;
elsif (line_oen_o(0) = '1' and line_o(0) = '0' and column_o(2) = '1') then
led_color(2) <= GREEN;
else
led_color(2) <= UNDEF;
end if;
if (line_oen_o(0) = '0' or (line_oen_o(0) = '1' and line_o(0) = column_o(3))) then
led_color(3) <= OFF;
elsif (line_oen_o(0) = '1' and line_o(0) = '1' and column_o(3) = '0') then
led_color(3) <= RED;
elsif (line_oen_o(0) = '1' and line_o(0) = '0' and column_o(3) = '1') then
led_color(3) <= GREEN;
else
led_color(3) <= UNDEF;
end if;
if (line_oen_o(1) = '0' or (line_oen_o(1) = '1' and line_o(1) = column_o(0))) then
led_color(4) <= OFF;
elsif (line_oen_o(1) = '1' and line_o(1) = '1' and column_o(0) = '0') then
led_color(4) <= RED;
elsif (line_oen_o(1) = '1' and line_o(1) = '0' and column_o(0) = '1') then
led_color(4) <= GREEN;
else
led_color(4) <= UNDEF;
end if;
if (line_oen_o(1) = '0' or (line_oen_o(1) = '1' and line_o(1) = column_o(1))) then
led_color(5) <= OFF;
elsif (line_oen_o(1) = '1' and line_o(1) = '1' and column_o(1) = '0') then
led_color(5) <= RED;
elsif (line_oen_o(1) = '1' and line_o(1) = '0' and column_o(1) = '1') then
led_color(5) <= GREEN;
else
led_color(5) <= UNDEF;
end if;
if (line_oen_o(1) = '0' or (line_oen_o(1) = '1' and line_o(1) = column_o(2))) then
led_color(6) <= OFF;
elsif (line_oen_o(1) = '1' and line_o(1) = '1' and column_o(2) = '0') then
led_color(6) <= RED;
elsif (line_oen_o(1) = '1' and line_o(1) = '0' and column_o(2) = '1') then
led_color(6) <= GREEN;
else
led_color(6) <= UNDEF;
end if;
if (line_oen_o(1) = '0' or (line_oen_o(1) = '1' and line_o(1) = column_o(3))) then
led_color(7) <= OFF;
elsif (line_oen_o(1) = '1' and line_o(1) = '1' and column_o(3) = '0') then
led_color(7) <= RED;
elsif (line_oen_o(1) = '1' and line_o(1) = '0' and column_o(3) = '1') then
led_color(7) <= GREEN;
else
led_color(7) <= UNDEF;
end if;
end process p_led_color_check;
-- Stimulus process
stim_proc : process
begin
-- hold reset state for 1 us.
rst_n_i <= '0';
wait for 1 us;
rst_n_i <= '1';
wait for 100 ns;
wait until rising_edge(clk_i);
led_intensity_i <= std_logic_vector(to_unsigned(100, led_intensity_i'length));
led_state_i(1 downto 0) <= c_LED_RED;
led_state_i(3 downto 2) <= c_LED_OFF;
led_state_i(5 downto 4) <= c_LED_RED_GREEN;
led_state_i(7 downto 6) <= c_LED_OFF;
led_state_i(9 downto 8) <= c_LED_GREEN;
led_state_i(11 downto 10) <= c_LED_OFF;
led_state_i(13 downto 12) <= c_LED_OFF;
led_state_i(15 downto 14) <= c_LED_RED_GREEN;
wait for 20 ms;
wait until rising_edge(clk_i);
led_intensity_i <= std_logic_vector(to_unsigned(50, led_intensity_i'length));
wait for 20 ms;
wait until rising_edge(clk_i);
led_intensity_i <= std_logic_vector(to_unsigned(10, led_intensity_i'length));
wait for 20 ms;
wait until rising_edge(clk_i);
led_intensity_i <= std_logic_vector(to_unsigned(0, led_intensity_i'length));
wait for 20 ms;
wait until rising_edge(clk_i);
led_intensity_i <= std_logic_vector(to_unsigned(120, led_intensity_i'length));
wait;
end process;
end tb;
hdl/top/bicolor_led_test/wave.do deleted 100644 → 0
View file @ 454b1dbb
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /bicolor_led_ctrl_tb/uut/rst_n_i
add wave -noupdate /bicolor_led_ctrl_tb/uut/clk_i
add wave -noupdate /bicolor_led_ctrl_tb/uut/led_state_i
add wave -noupdate -radix unsigned /bicolor_led_ctrl_tb/uut/led_intensity_i
add wave -noupdate /bicolor_led_ctrl_tb/uut/line_o(0)
add wave -noupdate /bicolor_led_ctrl_tb/uut/line_oen_o(0)
add wave -noupdate /bicolor_led_ctrl_tb/uut/line_o(1)
add wave -noupdate /bicolor_led_ctrl_tb/uut/line_oen_o(1)
add wave -noupdate /bicolor_led_ctrl_tb/uut/column_o(3)
add wave -noupdate /bicolor_led_ctrl_tb/uut/column_o(2)
add wave -noupdate /bicolor_led_ctrl_tb/uut/column_o(1)
add wave -noupdate /bicolor_led_ctrl_tb/uut/column_o(0)
add wave -noupdate -divider internals
add wave -noupdate -radix unsigned /bicolor_led_ctrl_tb/uut/refresh_rate_cnt
add wave -noupdate /bicolor_led_ctrl_tb/uut/refresh_rate
add wave -noupdate /bicolor_led_ctrl_tb/uut/line_oen_cnt
add wave -noupdate /bicolor_led_ctrl_tb/uut/line_oen
add wave -noupdate /bicolor_led_ctrl_tb/uut/line_ctrl
add wave -noupdate -radix unsigned /bicolor_led_ctrl_tb/uut/intensity_ctrl_cnt
add wave -noupdate /bicolor_led_ctrl_tb/uut/intensity_ctrl
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {281251037500 ps} 0}
configure wave -namecolwidth 295
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {279730374924 ps} {301066822373 ps}
hdl/top/ddr_test/Manifest.py deleted 100644 → 0
View file @ 454b1dbb
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0
files = [ "svec_afpga_top.vhd",
"svec_v1_afpga.ucf",
"csr.vhd",
"wb_addr_decoder.vhd",
"../bicolor_led_test/bicolor_led_ctrl.vhd",
"../bicolor_led_test/bicolor_led_ctrl_pkg.vhd"]
"""
fetchto = "ip_cores"
modules = {
"git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git" ],
"svn" : [ "http://svn.ohwr.org/ddr3-sp6-core/trunk/hdl",
"http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl"
]
}
"""
modules = {
"local" : [ "ip_cores/general-cores" ,
"ip_cores/ddr3-sp6-core/trunk/hdl",
"ip_cores/vme64x-core/trunk/hdl/vme64x-core/rtl" ]
}
hdl/top/ddr_test/csr.htm deleted 100644 → 0
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hdl/top/ddr_test/csr.vhd deleted 100644 → 0
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hdl/top/ddr_test/csr.wb deleted 100644 → 0
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peripheral {
name = "Control and status registers";
description = "Wishbone slave for control and status registers";
hdl_entity = "csr";
prefix = "csr";
reg {
name = "Carrier informations";
prefix = "carrier";
field {
name = "PCB revision";
description = "Binary coded PCB layout revision.";
prefix = "pcb_rev";
type = SLV;
size = 5;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reserved register";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 11;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Carrier type";
description = "Carrier type identifier";
prefix = "type";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Bitstream type";
prefix = "bitstream_type";
field {
name = "Bitstream type";
description = "Bitstream (firmware) type, unsigned 32-bit number.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Bitstream date";
prefix = "bitstream_date";
field {
name = "Bitstream date";
description = "Bitstream generation date, unsigned 32-bit UTC time.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Status";
prefix = "stat";
field {
name = "FMC slot 1 presence";
description = "0: FMC slot 1 is populated\n1: FMC 1 slot is not populated.";
prefix = "fmc1_pres";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "FMC slot 2 presence";
description = "0: FMC slot 2 is populated\n1: FMC 2 slot is not populated.";
prefix = "fmc2_pres";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "System clock PLL status";
description = "0: not locked\n1: locked.";
prefix = "sys_pll_lck";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "DDR3 bank4 calibration status";
description = "0: not done\n1: done.";
prefix = "ddr3_bank4_cal_done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "DDR3 bank5 calibration status";
description = "0: not done\n1: done.";
prefix = "ddr3_bank5_cal_done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "GPIO inputs";
description = "GPIO inputs value";
prefix = "gpio_in";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 23;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Control";
prefix = "ctrl";
field {
name = "Automatic front panel LEDs";
description = "Automatic front panel LEDs control";
prefix = "fp_leds_auto";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Front panel LEDs";
description = "Front panel LEDs control";
prefix = "fp_leds";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Front panel LED intensity";
description = "Front panel LED intensity in %";
prefix = "fp_led_int";
type = SLV;
size = 7;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "GPIO 1 direction";
description = "GPIO 1 dircetion\n0 = input\n 1 = output";
prefix = "gpio_1_dir";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "GPIO 2 direction";
description = "GPIO 2 dircetion\n0 = input\n 1 = output";
prefix = "gpio_2_dir";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "GPIO 3 and 4 direction";
description = "GPIO 3 and 4 dircetion\n0 = input\n 1 = output";
prefix = "gpio_34_dir";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "GPIO outputs";
description = "GPIO ouputs value";
prefix = "gpio_out";
type = SLV;
size = 4;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
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-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: wishbone address decoder
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 02-08-2011
--
-- version: 0.1
--
-- description: Provides a simple wishbone address decoder.
-- Splits the memory windows into equal parts.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- last changes:
--------------------------------------------------------------------------------
-- TODO:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity wb_addr_decoder is
generic
(
g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address)
g_WB_SLAVES_NB : integer := 2
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i : in std_logic_vector(31 downto 0); -- Address
wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out
wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wbm_stb_i : in std_logic; -- Strobe
wbm_we_i : in std_logic; -- Write
wbm_cyc_i : in std_logic; -- Cycle
wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in
wbm_ack_o : out std_logic; -- Acknowledge
wbm_stall_o : out std_logic; -- Stall
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o : out std_logic_vector(31 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge
wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall
);
end wb_addr_decoder;
architecture behaviour of wb_addr_decoder is
-----------------------------------------------------------------------------
-- Conatants declaration
-----------------------------------------------------------------------------
constant c_RST_ACTIVE : std_logic := '0';
-----------------------------------------------------------------------------
-- Functions declaration
-----------------------------------------------------------------------------
-- Returns log of 2 of a natural number
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
-- Wishbone
signal s_wb_periph_addr : std_logic_vector(log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
signal wb_periph_addr : std_logic_vector(log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
signal s_wb_periph_select : std_logic_vector((2**s_wb_periph_addr'length)-1 downto 0);
signal s_wb_ack_muxed : std_logic;
signal wb_ack_t : std_logic;
signal s_wb_dat_i_muxed : std_logic_vector(31 downto 0);
signal s_wb_cyc_demuxed : std_logic_vector(g_WB_SLAVES_NB-1 downto 0);
signal wb_adr_t : std_logic_vector(g_WINDOW_SIZE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
begin
------------------------------------------------------------------------------
-- Wishbone master address decoding
------------------------------------------------------------------------------
-- Take the first N bits of the address to select the active wb peripheral
-- g_WINDOW_SIZE represents 32-bit word address window
s_wb_periph_addr <= wbm_adr_i(g_WINDOW_SIZE-1 downto g_WINDOW_SIZE-log2_ceil(g_WB_SLAVES_NB));
-----------------------------------------------------------------------------
-- One-hot decode function, s_wb_periph_select <= onehot_decode(s_wb_periph_addr);
-----------------------------------------------------------------------------
onehot_decode : process(s_wb_periph_addr)
variable v_onehot : std_logic_vector((2**s_wb_periph_addr'length)-1 downto 0);
variable v_index : integer range 0 to (2**s_wb_periph_addr'length)-1;
begin
v_onehot := (others => '0');
v_index := 0;
for i in s_wb_periph_addr'range loop
if (s_wb_periph_addr(i) = '1') then
v_index := 2*v_index+1;
else
v_index := 2*v_index;
end if;
end loop;
v_onehot(v_index) := '1';
s_wb_periph_select <= v_onehot;
end process onehot_decode;
-- Register multiplexed ack and data + periph address
p_wb_in_regs : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
wb_periph_addr <= (others => '0');
wbm_dat_o <= (others => '0');
wb_ack_t <= '0';
elsif rising_edge(clk_i) then
wb_periph_addr <= s_wb_periph_addr;
wbm_dat_o <= s_wb_dat_i_muxed;
wb_ack_t <= s_wb_ack_muxed;
end if;
end process p_wb_in_regs;
wbm_ack_o <= wb_ack_t;
-- Select ack line of the active peripheral
p_ack_mux : process (wb_ack_i, wb_periph_addr)
begin
if (to_integer(unsigned(wb_periph_addr)) < g_WB_SLAVES_NB) then
s_wb_ack_muxed <= wb_ack_i(to_integer(unsigned(wb_periph_addr)));
else
s_wb_ack_muxed <= '0';
end if;
end process p_ack_mux;
-- Select stall line of the active peripheral
p_stall_mux : process (wb_stall_i, s_wb_periph_addr)
begin
if (to_integer(unsigned(s_wb_periph_addr)) < g_WB_SLAVES_NB) then
wbm_stall_o <= wb_stall_i(to_integer(unsigned(s_wb_periph_addr)));
else
wbm_stall_o <= '0';
end if;
end process p_stall_mux;
-- Select input data of the active peripheral
p_din_mux : process (wb_dat_i, wb_periph_addr)
begin
if (to_integer(unsigned(wb_periph_addr)) < g_WB_SLAVES_NB) then
s_wb_dat_i_muxed <=
wb_dat_i(31+(32*to_integer(unsigned(wb_periph_addr))) downto 32*to_integer(unsigned(wb_periph_addr)));
else
s_wb_dat_i_muxed <= (others => 'X');
end if;
end process p_din_mux;
-- Assert the cyc line of the selected peripheral
gen_cyc_demux : for i in 0 to g_WB_SLAVES_NB-1 generate
s_wb_cyc_demuxed(i) <= wbm_cyc_i and s_wb_periph_select(i) and not(wb_ack_t);
end generate gen_cyc_demux;
-- Slaves wishbone bus outputs
wb_dat_o <= wbm_dat_i;
wb_stb_o <= wbm_stb_i;
wb_we_o <= wbm_we_i;
wb_sel_o <= wbm_sel_i;
wb_cyc_o <= s_wb_cyc_demuxed;
-- extend address bus to 32-bit
wb_adr_t <= wbm_adr_i(g_WINDOW_SIZE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
wb_adr_o(wb_adr_t'left downto 0) <= wb_adr_t;
wb_adr_o(31 downto wb_adr_t'left+1) <= (others => '0');
end behaviour;
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#!/usr/bin/python
# Matthieu Cattin 2012
import re, sys
# Export netlist from Altium Designer in "Calay" format
NETLIST_FILENAME = "svec_v0.net"
UCF_FILENAME = "svec_v0.ucf"
PART_DESIGNATOR = "IC19"
IGNORED_NETNAMES = ["GND", "P3V3", "P2V5","P1V5", "P1V2", "P1V8",
"MTG_AVC_A", "MTG_AVC_B", "VREF_DDR3",
"FMC1_VREFAM2C", "FMC2_VREFAM2C"]
IOSTANDARD = "LVCMOS33"
filename = raw_input("Enter the input netlist filename (Must be Calay format!): ")
if filename != "":
NETLIST_FILENAME = filename
try:
net = open(NETLIST_FILENAME,"r")
print "%s netlist opened." % NETLIST_FILENAME
except:
print "ERROR %s file doesn't exist!" % NETLIST_FILENAME
sys.exit()
filename = raw_input("Enter the output .ucf filename: ")
if filename != "":
UCF_FILENAME = filename
try:
ucf = open(UCF_FILENAME+".raw","w")
print "%s .ucf opened." % UCF_FILENAME
except:
print "ERROR %s file doesn't exist!" % UCF_FILENAME
part = raw_input("Enter the part designator: ")
if part != "":
PART_DESIGNATOR = part
print "The part %s has been selected for ucf generation." % PART_DESIGNATOR
pin_cnt = 0
# Iterate over lines in netlist file
for line in net:
# Remove non-alphanumerical char
line = re.sub(r'[^\w]', ' ', line)
# Split line into strings
ln = line.split()
for s in ln:
# Look for lines containing the given part designator
if (ln[0] != s) and (PART_DESIGNATOR in s) and not(ln[0] in IGNORED_NETNAMES) and not(re.match("Net", ln[0])):
pin_cnt += 1
#print "%s %s %s" % (s, ln[0], ln[ln.index(s)+1])
ucf.write("NET \""+ln[0].lower()+"\" LOC = "+ln[ln.index(s)+1]+";\n")
if pin_cnt == 0:
print " Sorry, no pin found in %s" % (PART_DESIGNATOR)
if pin_cnt == 1:
print " => %d pin found in %s" % (pin_cnt, PART_DESIGNATOR)
else:
print " => %d pins found in %s" % (pin_cnt, PART_DESIGNATOR)
yesno = ""
while (yesno.lower() != 'y') and (yesno.lower() != 'n'):
yesno = raw_input("Do you want to generate default IOSTANDARD [y/n]: ")
if yesno == 'y':
net = open(NETLIST_FILENAME,"r")
ucf.write("\n\n\n\n")
# Iterate over lines in netlist file
for line in net:
# Remove non-alphanumerical char
line = re.sub(r'[^\w]', ' ', line)
# Split line into strings
ln = line.split()
for s in ln:
# Look for lines containing the given part designator
if (ln[0] != s) and (PART_DESIGNATOR in s) and not(ln[0] in IGNORED_NETNAMES) and not(re.match("Net", ln[0])):
# print "%s %s %s" % (s, ln[0], ln[ln.index(s)+1])
ucf.write("NET \""+ln[0].lower()+"\" IOSTANDARD = \""+ IOSTANDARD +"\";\n")
net.close()
ucf.close()
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