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Simple VME FMC Carrier SVEC
Commit ea24fca9 authored by Tristan Gingold's avatar Tristan Gingold
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Add a testbench for the vmecore_test board.

parent 5128aee2
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hdl/sim/vhdl_sim/Manifest.py 0 → 100644
View file @ ea24fca9
files = ["vme64x_sim_pkg.vhd"]
hdl/sim/vhdl_sim/vme64x_sim_pkg.vhd 0 → 100644
View file @ ea24fca9
This diff is collapsed.
hdl/testbench/tb_vmecore_test/Manifest.py 0 → 100644
View file @ ea24fca9
action = "simulation"
target = "xilinx"
sim_tool = "ghdl"
sim_top = "tb_vmecore_test"
vcom_opt = "-93 -mixedsvvh"
ghdl_opt = "-fsynopsys"
svec_template_ucf = []
syn_device = "xc6slx150t" # For rams.
board = "svec"
ctrls = ["bank4_64b_32b"]
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
#include_dirs=[fetchto + "/vme64x-core/hdl/sim/vme64x_bfm",
# fetchto + "/general-cores/sim"]
files = [ "buildinfo_pkg.vhd", "tb_vmecore_test.vhd"]
modules = {
"local" : [
"../../sim/vhdl_sim",
"../../top/vmecore_test" ],
"git" : [
# "https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/vme64x-core.git",
# "https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
hdl/testbench/tb_vmecore_test/tb_vmecore_test.vhd 0 → 100644
View file @ ea24fca9
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pkg.all;
use work.vme64x_sim_pkg.all;
entity tb_vmecore_test is
end tb_vmecore_test;
architecture behav of tb_vmecore_test is
signal rst_n_i : std_logic;
signal clk_20m_vcxo_i : std_logic := '0';
signal vme_write_n_i : std_logic;
signal vme_sysreset_n_i : std_logic;
signal vme_retry_oe_o : std_logic;
signal vme_retry_n_o : std_logic;
signal vme_lword_n_b : std_logic;
signal vme_iackout_n_o : std_logic;
signal vme_iackin_n_i : std_logic;
signal vme_iack_n_i : std_logic;
signal vme_gap_i : std_logic;
signal vme_dtack_oe_o : std_logic;
signal vme_dtack_n_o : std_logic;
signal vme_ds_n_i : std_logic_vector(1 downto 0);
signal vme_data_oe_n_o : std_logic;
signal vme_data_dir_o : std_logic;
signal vme_berr_o : std_logic;
signal vme_as_n_i : std_logic;
signal vme_addr_oe_n_o : std_logic;
signal vme_addr_dir_o : std_logic;
signal vme_irq_o : std_logic_vector(7 downto 1);
signal vme_ga_i : std_logic_vector(4 downto 0);
signal vme_data_b : std_logic_vector(31 downto 0);
signal vme_am_i : std_logic_vector(5 downto 0);
signal vme_addr_b : std_logic_vector(31 downto 1);
signal pcbrev_i : std_logic_vector(4 downto 0);
signal fp_led_line_oen_o : std_logic_vector(1 downto 0);
signal fp_led_line_o : std_logic_vector(1 downto 0);
signal fp_led_column_o : std_logic_vector(3 downto 0);
signal fp_gpio1_b : std_logic;
signal fp_gpio2_b : std_logic;
signal fp_gpio3_b : std_logic;
signal fp_gpio4_b : std_logic;
signal fp_term_en_o : std_logic_vector(4 downto 1);
signal fp_gpio1_a2b_o : std_logic;
signal fp_gpio2_a2b_o : std_logic;
signal fp_gpio34_a2b_o : std_logic;
signal vme_in : t_vme64x_in;
signal vme_out : t_vme64x_out;
signal vme_timeout : boolean := false;
signal stop : boolean := false;
begin
-- Clock.
process
begin
clk_20m_vcxo_i <= '0';
wait for 25 ns;
clk_20m_vcxo_i <= '1';
wait for 25 ns;
if stop then
wait;
end if;
end process;
process
is
procedure dump32 (base : natural; nword : natural)
is
variable addr : std_logic_vector (31 downto 0);
variable d32 : lword_t;
begin
for i in 0 to nword - 1 loop
addr := std_logic_vector(to_unsigned(base + i * 4, 32));
read32 (vme_in, vme_out, vme_timeout, x"00_10_00_00" or addr,
c_AM_A24, d32);
write(output, hex(addr) & ": " & hex(d32) & LF);
end loop;
end dump32;
variable d8 : byte_t;
variable d16 : word_t;
variable d32 : lword_t;
begin
-- Each scenario starts with a reset.
-- VME reset
report "VME reset";
vme_in.ga <= '1' & slave_ga;
rst_n_i <= '0';
VME_in.RST_n <= '0';
VME_in.AS_n <= '1';
VME_in.ADDR <= (others => '1');
VME_in.AM <= (others => '1');
VME_in.DS_n <= "11";
VME_in.iackin_n <= '1';
wait for 40 ns;
VME_in.RST_n <= '1';
rst_n_i <= '1';
wait for 40 ns;
report "Set ADER";
-- Set ADER
write8_conf (vme_in, vme_out, vme_timeout, x"7_ff77", x"10");
write8_conf (vme_in, vme_out, vme_timeout, x"7_ff7f", c_AM_A24 & "00");
read8_conf (vme_in, vme_out, vme_timeout, x"7_ff77", d8);
assert d8 = x"10" report "bad ADER0 value" severity error;
report "Set ENable";
-- Enable card
write8_conf (vme_in, vme_out, vme_timeout, x"7_fffb", b"0001_0000");
read8_conf (vme_in, vme_out, vme_timeout, x"7_fffb", d8);
assert d8 = b"0001_0000" report "module must be enabled"
severity error;
report "read data: " & hex (d8);
-- dump_CR (vme_in, vme_out, vme_timeout);
report "Dump patterns";
dump32 (16#c000#, 4);
if false then
report "VME CR";
dump_CR (vme_in, vme_out, vme_timeout);
end if;
report "done";
stop <= true;
wait;
end process;
vme_data_b <= vme_in.data when not (vme_out.data_oe_n = '0'
and vme_out.data_dir = '1')
else (others => 'H');
vme_out.data <= vme_data_b;
vme_addr_b <= vme_in.addr when not (vme_out.addr_oe_n = '0'
and vme_out.addr_dir = '1')
else (others => 'H');
vme_out.addr <= vme_addr_b;
vme_lword_n_b <= vme_in.lword_n when not (vme_out.addr_oe_n = '0'
and vme_out.addr_dir = '1')
else 'H';
vme_out.lword_n <= vme_lword_n_b;
-- ga is inverted.
vme_ga_i <= not vme_in.ga (4 downto 0);
vme_gap_i <= vme_in.ga(5);
vme_out.berr_n <= not vme_berr_o;
dut: entity work.svec_vmecore_test_top
generic map (
g_SIMULATION => True
)
port map (
rst_n_i => rst_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
vme_gap_i => vme_gap_i,
vme_ga_i => vme_ga_i,
vme_as_n_i => vme_in.as_n,
vme_sysreset_n_i => vme_in.rst_n,
vme_write_n_i => vme_in.write_n,
vme_am_i => vme_in.am,
vme_ds_n_i => vme_in.ds_n,
vme_iack_n_i => vme_in.iack_n,
vme_iackin_n_i => vme_in.iackin_n,
vme_iackout_n_o => vme_out.iackout_n,
vme_dtack_n_o => vme_out.dtack_n,
vme_dtack_oe_o => vme_out.dtack_oe,
vme_data_dir_o => vme_out.data_dir,
vme_data_oe_n_o => vme_out.data_oe_n,
vme_addr_dir_o => vme_out.addr_dir,
vme_addr_oe_n_o => vme_out.addr_oe_n,
vme_retry_n_o => vme_out.retry_n,
vme_retry_oe_o => vme_out.retry_oe,
vme_berr_o => vme_berr_o,
vme_irq_o => vme_irq_o,
vme_lword_n_b => vme_lword_n_b,
vme_data_b => vme_data_b,
vme_addr_b => vme_addr_b,
fp_led_line_oen_o => fp_led_line_oen_o,
fp_led_line_o => fp_led_line_o,
fp_led_column_o => fp_led_column_o);
end behav;
hdl/top/vmecore_test/svec_vmecore_test_top.vhd
View file @ ea24fca9
......@@ -7,7 +7,7 @@
-- Author(s) : Tristan Gingold <tristan.gingold@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-09-19
-- Last update: 2020-03-12
-- Last update: 2020-05-29
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the test design .
......@@ -48,6 +48,9 @@ library unisim;
use unisim.vcomponents.all;
entity svec_vmecore_test_top is
generic (
g_SIMULATION : boolean := False
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
......@@ -199,80 +202,94 @@ architecture top of svec_vmecore_test_top is
signal sys_locked : std_logic;
begin -- architecture top
p_powerup_reset : process(clk_sys)
begin
if rising_edge(clk_sys) then
if(vme_sysreset_n_i = '0' or rst_n_i = '0') then
powerup_rst_n <= '0';
elsif sys_locked = '1' then
if(powerup_reset_cnt = "11111111") then
powerup_rst_n <= '1';
gen_pll: if not g_SIMULATION generate
p_powerup_reset : process(clk_sys)
begin
if rising_edge(clk_sys) then
if(vme_sysreset_n_i = '0' or rst_n_i = '0') then
powerup_rst_n <= '0';
elsif sys_locked = '1' then
if(powerup_reset_cnt = "11111111") then
powerup_rst_n <= '1';
else
powerup_rst_n <= '0';
powerup_reset_cnt <= powerup_reset_cnt + 1;
end if;
else
powerup_rst_n <= '0';
powerup_reset_cnt <= powerup_reset_cnt + 1;
powerup_reset_cnt <= "00000000";
end if;
else
powerup_rst_n <= '0';
powerup_reset_cnt <= "00000000";
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Clock distribution/PLL and reset
-------------------------------------------------------------------------------
-- Input is 20Mhz
U_cmp_sys_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50, -- 1Ghz
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8, -- 2*62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 2*62.5 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_sys,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open, -- pllout_clk_sys,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_locked,
RST => '0',
CLKFBIN => pllout_clk_fb_sys,
CLKIN => clk_20m_vcxo_buf);
U_Sync_Reset : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => powerup_rst_n,
synced_o => local_reset_n);
U_cmp_clk_vcxo_buf : BUFG
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
U_cmp_clk_sys_buf : BUFG
port map (
O => clk_sys,
I => pllout_clk_sys);
end process;
--------------------------------------------------------------------------
-- Clock distribution/PLL and reset
--------------------------------------------------------------------------
-- Input is 20Mhz
U_cmp_sys_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50, -- 1Ghz
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8, -- 2*62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 2*62.5 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_sys,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open, -- pllout_clk_sys,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_locked,
RST => '0',
CLKFBIN => pllout_clk_fb_sys,
CLKIN => clk_20m_vcxo_buf);
U_Sync_Reset : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => powerup_rst_n,
synced_o => local_reset_n);
U_cmp_clk_vcxo_buf : BUFG
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
U_cmp_clk_sys_buf : BUFG
port map (
O => clk_sys,
I => pllout_clk_sys);
end generate;
gen_nopll: if g_SIMULATION generate
process
begin
clk_sys <= '0';
wait for 8 ns;
clk_sys <= '1';
wait for 8 ns;
end process;
local_reset_n <= '0', '1' after 16 ns;
end generate;
-----------------------------------------------------------------------------
-- VME64x Core and buffers
......
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