hdl/top/golden: updated synthesis descriptor

dc70a950 · Tomasz Wlostowski · 63c8def1 · dc70a950
Commit dc70a950 authored Feb 07, 2014 by Tomasz Wlostowski
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synthesis_descriptor.vhd hdl/top/golden/synthesis_descriptor.vhd +3 -3

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--- a/hdl/top/golden/synthesis_descriptor.vhd
+++ b/hdl/top/golden/synthesis_descriptor.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2013-04-16
-- Last update: 2013-04-16
+-- Last update: 2014-02-04
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -43,10 +43,10 @@ package synthesis_descriptor is
 constant c_sdb_synthesis_info : t_sdb_synthesis :=
  (
    syn_module_name => "svec-golden     ",
-    syn_commit_id => "00000000000000000000000000000000",
+    syn_commit_id => "daf244bfc22002fbf68514441cd45c23",
    syn_tool_name => "ISE     ",
    syn_tool_version => x"00000133",
-    syn_date => x"20140203",
+    syn_date => x"20140204",
    syn_username => "twlostow       ");

 constant c_sdb_repo_url : t_sdb_repo_url :=