[hdl] move UCFs to syn/common restructure DDR constraints

d8f4adcc · Dimitris Lampridis · 53203b3c · d8f4adcc · d8f4adcc · d8f4adcc
Commit d8f4adcc authored Aug 02, 2019 by Dimitris Lampridis
10 changed files
--- a/Manifest.py
+++ b/Manifest.py
 modules = { "local" : [ "hdl/rtl" ] }
+
+if action == "synthesis":
+    modules["local"].append("hdl/syn/common")
--- a/hdl/rtl/Manifest.py
+++ b/hdl/rtl/Manifest.py
-# User should define the variable svec_template_ucf
-
-files = ["svec_template_regs.vhd",
-         "svec_template_wr.vhd", "svec_template_common.ucf" ]
-
-ucf_dict = {'ddr4': "svec_template_ddr4.ucf",
-            'ddr5': "svec_template_ddr5.ucf",
-            'wr':   "svec_template_wr.ucf",
-            'led':  "svec_template_led.ucf",
-            'gpio': "svec_template_gpio.ucf" }
-for p in svec_template_ucf:
-    f = ucf_dict.get(p, None)
-    assert f is not None, "unknown name {} in 'svec_template_ucf'".format(p)
-    files.append(f)
+files = [
+    "svec_template_regs.vhd",
+    "svec_template_wr.vhd",
+]
--- a/hdl/syn/common/Manifest.py
+++ b/hdl/syn/common/Manifest.py
+# User should define the variable svec_template_ucf
+
+files = [ "svec_template_common.ucf" ]
+
+ucf_dict = {
+    'ddr4': "svec_template_ddr4.ucf",
+    'ddr5': "svec_template_ddr5.ucf",
+    'wr':   "svec_template_wr.ucf",
+    'led':  "svec_template_led.ucf",
+    'gpio': "svec_template_gpio.ucf",
+}
+
+for p in svec_template_ucf:
+    f = ucf_dict.get(p, None)
+    assert f is not None, "unknown name {} in 'svec_template_ucf'".format(p)
+    if p == 'ddr4' or p == 'ddr5':
+        files.append('svec_template_ddr_common.ucf')
+    files.append(f)
--- a/hdl/rtl/svec_template_common.ucf
+++ b/hdl/rtl/svec_template_common.ucf
@@ -230,11 +230,9 @@ TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;

 NET "inst_svec_template/clk_sys_62m5" TNM_NET = sys_clk;
 NET "inst_svec_template/clk_ref_125m" TNM_NET = ref_clk;
-NET "inst_svec_template/clk_ddr_333m" TNM_NET = ddr_clk;

 TIMEGRP "ref_sync_ffs"  = "sync_ffs" EXCEPT "ref_clk";
 TIMEGRP "sys_sync_ffs"  = "sync_ffs" EXCEPT "sys_clk";
-TIMEGRP "ddr_sync_ffs"  = "sync_ffs" EXCEPT "ddr_clk";

 # Exceptions for crossings via gc_sync_ffs

@@ -242,7 +240,6 @@ NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";

 TIMESPEC TS_ref_sync_ffs  = FROM ref_clk TO "sys_sync_ffs"  TIG;
 TIMESPEC TS_sys_sync_ffs  = FROM sys_clk TO "sys_sync_ffs"  TIG;
-TIMESPEC TS_ddr_sync_ffs  = FROM ddr_clk TO "ddr_sync_ffs"  TIG;

 # Exceptions for crossings via gc_sync_register

@@ -250,8 +247,6 @@ NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";

 TIMEGRP "ref_sync_reg" = "sync_reg" EXCEPT "ref_clk";
 TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
-TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";

 TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "ref_sync_reg"  8ns  DATAPATHONLY;
 TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg"  16ns DATAPATHONLY;
-TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg"  3ns  DATAPATHONLY;
--- a/hdl/rtl/svec_template_ddr4.ucf
+++ b/hdl/rtl/svec_template_ddr4.ucf
@@ -73,23 +73,3 @@ NET "ddr4_ldqs_p_b" IN_TERM = NONE;
 NET "ddr4_ldqs_n_b" IN_TERM = NONE;
 NET "ddr4_udqs_p_b" IN_TERM = NONE;
 NET "ddr4_udqs_n_b" IN_TERM = NONE;
-
-#----------------------------------------
-# Xilinx MCB tweaks
-#----------------------------------------
-
-# These are suggested by the Xilinx-generated MCB.
-# More info in the UCF file found in the "user_design/par" of the generated core.
-NET "inst_svec_template/gen_with_ddr4.cmp_ddr_ctrl_bank/*/c?_pll_lock"                                     TIG;
-NET "inst_svec_template/gen_with_ddr4.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
-NET "inst_svec_template/gen_with_ddr4.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL"  TIG;
-#NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ"   TIG;
-
-#----------------------------------------
-# Cross-clock domain sync
-#----------------------------------------
-
-# Declaration of domains
-
-NET "inst_svec_template/gen_with_ddr4.cmp_ddr_ctrl_bank/*/memc?_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
-NET "inst_svec_template/gen_with_ddr4.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/ioi_drp_clk"        TNM_NET = ddr_clk;
--- a/hdl/rtl/svec_template_ddr5.ucf
+++ b/hdl/rtl/svec_template_ddr5.ucf
@@ -73,23 +73,3 @@ NET "ddr5_ldqs_p_b[*]" IN_TERM = NONE;
 NET "ddr5_ldqs_n_b[*]" IN_TERM = NONE;
 NET "ddr5_udqs_p_b[*]" IN_TERM = NONE;
 NET "ddr5_udqs_n_b[*]" IN_TERM = NONE;
-
-#----------------------------------------
-# Xilinx MCB tweaks
-#----------------------------------------
-
-# These are suggested by the Xilinx-generated MCB.
-# More info in the UCF file found in the "user_design/par" of the generated core.
-NET "inst_svec_template/gen_with_ddr5.cmp_ddr_ctrl_bank/*/c?_pll_lock"                                     TIG;
-NET "inst_svec_template/gen_with_ddr5.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
-NET "inst_svec_template/gen_with_ddr5.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL"  TIG;
-#NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ"   TIG;
-
-#----------------------------------------
-# Cross-clock domain sync
-#----------------------------------------
-
-# Declaration of domains
-
-NET "inst_svec_template/gen_with_ddr5.cmp_ddr_ctrl_bank/*/memc?_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
-NET "inst_svec_template/gen_with_ddr5.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/ioi_drp_clk"        TNM_NET = ddr_clk;
--- a/hdl/syn/common/svec_template_ddr_common.ucf
+++ b/hdl/syn/common/svec_template_ddr_common.ucf
+#----------------------------------------
+# Xilinx MCB tweaks
+#----------------------------------------
+
+# These are suggested by the Xilinx-generated MCB.
+# More info in the UCF file found in the "user_design/par" of the generated core.
+NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/c?_pll_lock"                                     TIG;
+NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
+NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL"  TIG;
+#NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ"   TIG;
+
+#----------------------------------------
+# Asynchronous resets
+#----------------------------------------
+
+# Ignore async reset to DDR controller
+NET "inst_svec_template/ddr_rst" TPTHRU = ddr_rst;
+TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
+
+#----------------------------------------
+# Cross-clock domain sync
+#----------------------------------------
+
+NET "inst_svec_template/clk_ddr_333m" TNM_NET = ddr_clk;
+
+NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
+NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/ioi_drp_clk"        TNM_NET = ddr_clk;
+
+# DDR does not use any sync modules
+
+#TIMEGRP "ddr_sync_ffs"  = "sync_ffs" EXCEPT "ddr_clk";
+
+#TIMESPEC TS_ddr_sync_ffs  = FROM ddr_clk TO "ddr_sync_ffs"  TIG;
+
+#TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";
+
+#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg"  3ns  DATAPATHONLY;
--- a/hdl/rtl/svec_template_gpio.ucf
+++ b/hdl/rtl/svec_template_gpio.ucf
--- a/hdl/rtl/svec_template_led.ucf
+++ b/hdl/rtl/svec_template_led.ucf
--- a/hdl/rtl/svec_template_wr.ucf
+++ b/hdl/rtl/svec_template_wr.ucf