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Simple VME FMC Carrier SVEC
Commit d68efe3b authored by Greg's avatar Greg
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99% of PCB done, schematics updated with post-routing changes

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circuit_board/SVEC/SVEC.OutJob
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circuit_board/SVEC/SVEC.PrjPcb
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circuit_board/SVEC/SVEC.PrjPcbStructure
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Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_AFPGA|SchDesignator=U_AFPGA|FileName=AFPGA.SchDoc|SymbolType=Normal|RawFileName=AFPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_AFPGA_power|SchDesignator=U_AFPGA_power|FileName=AFPGA_power.SchDoc|SymbolType=Normal|RawFileName=AFPGA_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_ClkGeneration|SchDesignator=U_ClkGeneration|FileName=ClkGeneration.SchDoc|SymbolType=Normal|RawFileName=ClkGeneration.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_DDR3_1|SchDesignator=U_DDR3_1|FileName=DDR3.SchDoc|SymbolType=Normal|RawFileName=DDR3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_DDR3_2|SchDesignator=U_DDR3_2|FileName=DDR3_2.SchDoc|SymbolType=Normal|RawFileName=DDR3_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_FmcConnectors|SchDesignator=U_FmcConnectors|FileName=FMC_CONNECTORS.SchDoc|SymbolType=Normal|RawFileName=FMC_CONNECTORS.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_fpga_gtp|SchDesignator=U_fpga_gtp|FileName=fpga_gtp.SchDoc|SymbolType=Normal|RawFileName=fpga_gtp.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_FrontPannel|SchDesignator=U_FrontPannel|FileName=FrontPannel.SchDoc|SymbolType=Normal|RawFileName=FrontPannel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_JTAG&CONFIG|SchDesignator=U_JTAG&CONFIG|FileName=JTAG&CONFIG.SchDoc|SymbolType=Normal|RawFileName=JTAG&CONFIG.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_PowerSupplies|SchDesignator=U_PowerSupplies|FileName=PowerSupplies.SchDoc|SymbolType=Normal|RawFileName=PowerSupplies.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_SFPGA|SchDesignator=U_SFPGA|FileName=SFPGA.SchDoc|SymbolType=Normal|RawFileName=SFPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_SFPGA_power|SchDesignator=U_SFPGA_power|FileName=SFPGA_power.SchDoc|SymbolType=Normal|RawFileName=SFPGA_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_USB|SchDesignator=U_USB|FileName=USB.SchDoc|SymbolType=Normal|RawFileName=USB.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_VmeConnectors|SchDesignator=U_VmeConnectors|FileName=VmeConnectors.SchDoc|SymbolType=Normal|RawFileName=VmeConnectors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_AFPGA|SchDesignator=U_AFPGA|FileName=AFPGA.SchDoc|SymbolType=Normal|RawFileName=AFPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_AFPGA_power|SchDesignator=U_AFPGA_power|FileName=AFPGA_power.SchDoc|SymbolType=Normal|RawFileName=AFPGA_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_ClkGeneration|SchDesignator=U_ClkGeneration|FileName=ClkGeneration.SchDoc|SymbolType=Normal|RawFileName=ClkGeneration.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_DDR3_1|SchDesignator=U_DDR3_1|FileName=DDR3.SchDoc|SymbolType=Normal|RawFileName=DDR3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_DDR3_2|SchDesignator=U_DDR3_2|FileName=DDR3_2.SchDoc|SymbolType=Normal|RawFileName=DDR3_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_FmcConnectors|SchDesignator=U_FmcConnectors|FileName=FMC_CONNECTORS.SchDoc|SymbolType=Normal|RawFileName=FMC_CONNECTORS.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_fpga_gtp|SchDesignator=U_fpga_gtp|FileName=fpga_gtp.SchDoc|SymbolType=Normal|RawFileName=fpga_gtp.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_FrontPanel|SchDesignator=U_FrontPanel|FileName=FrontPanel.SchDoc|SymbolType=Normal|RawFileName=FrontPanel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_JTAG&CONFIG|SchDesignator=U_JTAG&CONFIG|FileName=JTAG&CONFIG.SchDoc|SymbolType=Normal|RawFileName=JTAG&CONFIG.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_PowerSupplies|SchDesignator=U_PowerSupplies|FileName=PowerSupplies.SchDoc|SymbolType=Normal|RawFileName=PowerSupplies.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_SFPGA|SchDesignator=U_SFPGA|FileName=SFPGA.SchDoc|SymbolType=Normal|RawFileName=SFPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_SFPGA_power|SchDesignator=U_SFPGA_power|FileName=SFPGA_power.SchDoc|SymbolType=Normal|RawFileName=SFPGA_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_USB|SchDesignator=U_USB|FileName=USB.SchDoc|SymbolType=Normal|RawFileName=USB.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_VmeConnectors|SchDesignator=U_VmeConnectors|FileName=VmeConnectors.SchDoc|SymbolType=Normal|RawFileName=VmeConnectors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=TopLevelDocument|FileName=SVEC_TOP.SchDoc
Record=FPGA_COMPONENT|BaseComponentDesignator=IC19|DocumentName=AFPGA.SchDoc|LibraryReference=XC6SLX150T-2FGG900C|SubProjectPath= |Configuration= |Description=SPARTAN-6, FPGA, 900-Ball BGA, Commercial Grade, Pb-Free|NexusDeviceId=XC6SLX150T-2FGG900C|SubPartUniqueId1=NGIDIYWR|SubPartDocPath1=AFPGA.SchDoc|SubPartUniqueId2=FUNNCDPN|SubPartDocPath2=AFPGA.SchDoc|SubPartUniqueId3=QBXJFLEN|SubPartDocPath3=AFPGA.SchDoc|SubPartUniqueId4=JJOQTPQG|SubPartDocPath4=AFPGA.SchDoc|SubPartUniqueId5=DUYJDUAV|SubPartDocPath5=AFPGA.SchDoc|SubPartUniqueId6=MEKFUFMR|SubPartDocPath6=AFPGA.SchDoc|SubPartUniqueId7=EWTIHSSR|SubPartDocPath7=AFPGA.SchDoc|SubPartUniqueId8=VYVXECCI|SubPartDocPath8=DDR3.SchDoc|SubPartUniqueId9=HGYTKHSM|SubPartDocPath9=DDR3_2.SchDoc|SubPartUniqueId10=HVOTMCXP|SubPartDocPath10=FPGA_GTP.SchDoc|SubPartUniqueId11=DJFABCDT|SubPartDocPath11=FPGA_GTP.SchDoc|SubPartUniqueId12=SUEJCWVA|SubPartDocPath12=FPGA_GTP.SchDoc|SubPartUniqueId13=IJQHRHAL|SubPartDocPath13=FPGA_GTP.SchDoc|SubPartUniqueId14=RIFFUJKX|SubPartDocPath14=JTAG&CONFIG.SchDoc|SubPartUniqueId15=TNOTCNVT|SubPartDocPath15=AFPGA_power.SchDoc|SubPartUniqueId16=VINGWMCL|SubPartDocPath16=AFPGA_power.SchDoc|SubPartUniqueId17=KPAAVKWI|SubPartDocPath17=AFPGA_power.SchDoc|SubPartUniqueId18=TWWKQKGX|SubPartDocPath18=AFPGA_power.SchDoc
Record=FPGA_COMPONENT|BaseComponentDesignator=IC40|DocumentName=SFPGA.SchDoc|LibraryReference=XC6SLX9-2FTG256C|SubProjectPath= |Configuration= |Description=Spartan-6 LX 1.2V FPGA, 186 User I/Os, 256-Ball Fine-Pitch Thin BGA (1.0mm Pitch), Speed Grade 2, Commercial Grade, Pb-Free|NexusDeviceId=XC6SLX9-2FTG256C|SubPartUniqueId1=QTOJQSMD|SubPartDocPath1=SFPGA.SchDoc|SubPartUniqueId2=AOYRMHFT|SubPartDocPath2=SFPGA.SchDoc|SubPartUniqueId3=OLSNOCAD|SubPartDocPath3=SFPGA.SchDoc|SubPartUniqueId4=LFMNKHSD|SubPartDocPath4=SFPGA.SchDoc|SubPartUniqueId5=ODYKENES|SubPartDocPath5=JTAG&CONFIG.SchDoc|SubPartUniqueId6=WVUDHYEK|SubPartDocPath6=SFPGA_power.SchDoc|SubPartUniqueId7=FATYVDMF|SubPartDocPath7=SFPGA_power.SchDoc
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