Commit d1a17593 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

hdl,software: svec-flasher tool & documentation improvements

parent 97b766b9
......@@ -181,10 +181,67 @@ Only A32/A24/D32/CSR address modifiers are supported.
@item @code{xwb_gpio_port} @tab @code{0x13000} @tab @code{general-cores} @tab GPIO port for accessing FMC1/2 presence lines.
@end multitable
@macro regsection{name}
@section \name\
@end macro
@page
@chapter Flashing the SVEC
@section Application FPGA Flash programming through VME
The SVEC Application FPGA can be programmed with the @code{svec-flasher} tool, located in @code{software/vme-flasher} subdirectory of the SVEC project repository. It requires a @code{.bin} format bitstream, that can be generated by Xilinx ISE by selecting ``Generate binary configuration file'' in @i{Generate Programming File} options.
The flasher requires the slot number as the first argument and the file with the bitstream as the second, just like in the example below:
@smallexample
# ./svec-flasher.L865 12 /lib/firmware/fmc/svec-golden.bin
Programming the Application FPGA flash with bitstream /lib/firmware/fmc/svec-golden.bin.
Programming page 7651/7651.
Verification...
Programming page 0/0.
Verification...
Programming OK.
@end smallexample
@b{Note 1:} Before programming the flash, please unload the SVEC kernel driver:
@smallexample
# rmmod svec
@end smallexample
@b{Note 2:} The flasher must be run as root.
@b{Note 3:} The card must be rebooted for the new bitstream to start working.
@section Updating the bootloader
Certain older SVEC cards have been shipped with the first version of the bootloader that does not support booting the AFPGA from the Flash memory. In order to use from the VME Flasher, an update is necessary. The procedure goes as follows:
@itemize
@item Download the updated bootloader @code{svec-bootloader-v2.mcs} from @uref{http://www.ohwr.org/projects/svec/files}.
@item Connect Xilinx JTAG programmer to the JTAG connector of the card to be updated.
@item Launch ISE iMPACT.
@item Double-Click ``Boundary Scan'' in the left pane (``iMPACT flows'').
@item Open the right-click menu in the main work area and select ``Initialize chain'' or press Ctrl+I.
@item Right click on the ``SPI/BPI ?'' box above the ``xc6slx9'' FPGA and select ``Add SPI/BPI Flash''.
@item Pick the @code{svec-bootloader-v2.mcs} file.
@item Select flash type: SPI PROM, M25P128, data width: 1.
@item Right click on the ``FLASH'' chip above the ``xc6slx9'' and select ``Program''. Select the ``Verify'' option and click OK.
@item If everything went fine, ``Programming succeeded'' message will appear.
@item Reboot the VME crate to use the new bootloader.
@end itemize
@b{Note:} Updating the bootloader does not require updating the drivers, as it is backwards-compatible.
@section Application FPGA Flash programming through JTAG
This method of programming may be useful during factory JTAG programming of SVECs, when both the bootloader and the application bitstream need to be loaded simultaneously. It requires a special flash image that contains both the bootloader and application bitstreams along with some SDB filesystem structures that allow the bootloader to correctly load the AFPGA file.
Preparing the flash image is straightforward:
@itemize
@item Copy your AFPGA bitstream (@code{.bin} format) to @code{software/sdb-flasher/fs/afpga.bin}.
@item Run the script: @code{software/sdb-flasher/build.sh}. The script will produce the file called @code{image.mcs}.
@item Program the Flash (@code{image.mcs}) via iMPACT, using the procedure described in the previous section.
@end itemize
@page
@chapter References
@enumerate
......
......@@ -36,7 +36,7 @@ FIFO 'Bitstream FIFO' control/status register
@item @code{0}
@tab W/O @tab
@code{START}
@tab @code{X} @tab
@tab @code{0} @tab
Start configuration
@item @code{1}
@tab R/O @tab
......@@ -56,23 +56,28 @@ Loader busy
@item @code{4}
@tab R/W @tab
@code{MSBF}
@tab @code{X} @tab
@tab @code{0} @tab
Byte order select
@item @code{5}
@tab W/O @tab
@code{SWRST}
@tab @code{X} @tab
@tab @code{0} @tab
Software resest
@item @code{6}
@tab W/O @tab
@code{EXIT}
@tab @code{X} @tab
@tab @code{0} @tab
Exit bootloader mode
@item @code{13...8}
@tab R/W @tab
@code{CLKDIV}
@tab @code{X} @tab
@tab @code{0} @tab
Serial clock divider
@item @code{21...14}
@tab R/O @tab
@code{VERSION}
@tab @code{X} @tab
Bootloader version
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
......@@ -91,7 +96,7 @@ Serial clock divider
@item @code{7...0}
@tab W/O @tab
@code{BTRIGR}
@tab @code{X} @tab
@tab @code{0} @tab
Trigger Sequence Input
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -110,7 +115,7 @@ SPI Data
@item @code{8}
@tab R/W @tab
@code{XFER}
@tab @code{X} @tab
@tab @code{0} @tab
SPI Start Transfer
@item @code{9}
@tab R/O @tab
......@@ -120,7 +125,7 @@ SPI Ready
@item @code{10}
@tab R/W @tab
@code{CS}
@tab @code{X} @tab
@tab @code{0} @tab
SPI Chip Select
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -149,12 +154,12 @@ Identification code
@item @code{1...0}
@tab W/O @tab
@code{XSIZE}
@tab @code{X} @tab
@tab @code{0} @tab
Entry size
@item @code{2}
@tab W/O @tab
@code{XLAST}
@tab @code{X} @tab
@tab @code{0} @tab
Last xfer
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -168,7 +173,7 @@ Last xfer
@item @code{31...0}
@tab W/O @tab
@code{XDATA}
@tab @code{X} @tab
@tab @code{0} @tab
Data
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -191,7 +196,7 @@ FIFO empty flag
@item @code{18}
@tab W/O @tab
@code{CLEAR_BUS}
@tab @code{X} @tab
@tab @code{0} @tab
FIFO clear
@item @code{7...0}
@tab R/O @tab
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : svec_xloader_wb.vhd
-- Author : auto-generated by wbgen2 from svec_xloader_wb.wb
-- Created : Fri Jan 25 14:55:57 2013
-- Created : Mon Sep 2 10:21:20 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE svec_xloader_wb.wb
......@@ -123,23 +123,16 @@ begin
sxldr_csr_exit_int <= wrdata_reg(6);
sxldr_csr_clkdiv_int <= wrdata_reg(13 downto 8);
end if;
rddata_reg(0) <= 'X';
rddata_reg(0) <= '0';
rddata_reg(1) <= regs_i.csr_done_i;
rddata_reg(2) <= regs_i.csr_error_i;
rddata_reg(3) <= regs_i.csr_busy_i;
rddata_reg(4) <= sxldr_csr_msbf_int;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(5) <= '0';
rddata_reg(6) <= '0';
rddata_reg(13 downto 8) <= sxldr_csr_clkdiv_int;
rddata_reg(21 downto 14) <= "00000010";
rddata_reg(7) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
......
......@@ -119,6 +119,15 @@ peripheral {
access_bus = READ_WRITE;
access_dev =READ_ONLY;
};
field {
name = "Bootloader version";
prefix = "VERSION";
type = CONSTANT;
size = 8;
value = 2;
}
};
reg {
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : sxldr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from svec_xloader_wb.wb
-- Created : Fri Jan 25 14:55:57 2013
-- Created : Mon Sep 2 10:21:20 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE svec_xloader_wb.wb
......
This diff is collapsed.
......@@ -11,6 +11,7 @@
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdlib.h>
#ifndef __MSDOS__
#include <unistd.h>
#endif
......@@ -199,7 +200,7 @@ int Dots, int Extended)
if ((Address + InBytes) > MaxOffset) {
if (Dots)
fputc('\n',stderr);
fprintf(stderr,"%s: Record address exceeded 0x%X.\n",
fprintf(stderr,"%s: Record address exceeded 0x%lX.\n",
Name,MaxOffset);
break;
}
......
......@@ -2,8 +2,8 @@
# A trivial script to build the SDB flash image for the SVEC. Requires sdb-tools installed in the system
cp ../../hdl/syn/sfpga_bootloader/svec_sfpga_top.bin fs/sfpga.bin
cp ../../hdl/syn/golden/svec_top.bin fs/afpga.bin
#cp ../../hdl/syn/sfpga_bootloader/svec_sfpga_top.bin fs/bootldr.bin
#cp ../../hdl/syn/golden/svec_top.bin fs/afpga.bin
gcc bin2vmf.c -o bin2vmf
gcc bin2ihex.c -o bin2ihex
gensdbfs fs image.bin
......
......@@ -8,7 +8,7 @@
device = 0x5fec
position = 0x500000
sfpga.bin
bootldr.bin
position = 0
afpga.bin
......
CFLAGS = -I../sveclib
OBJS = ../sveclib/libvmebus.o svec-flasher.o
CC = gcc
all: $(OBJS)
${CC} -o svec-flasher $(OBJS)
\ No newline at end of file
/*
* Copyright (C) 2013 CERN (www.cern.ch)
* Author: Tomasz Włostowski <tomasz.wlostowski@cern.ch>
*
* Released according to the GNU GPL, version 2 or any later version.
*
* svec-flasher: a trivial VME-SPI flasher application.
*/
#include <stdio.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <unistd.h>
#include <arpa/inet.h>
#include <libvmebus.h>
#include "sxldr_regs.h"
#define BOOTLOADER_BASE 0x70000
#define BOOTLOADER_VERSION 2
#define BOOTLOADER_BITSTREAM_BASE 0x100000
#define BOOTLOADER_SDB_BASE 0x500000
#define ID_M25P128 0x202018
#define FLASH_PAGE_SIZE 256
#define FLASH_SECTOR_SIZE 0x40000
#define FLASH_SIZE 0x1000000
/* M25Pxxx SPI flash commands */
#define FLASH_WREN 0x06
#define FLASH_WRDI 0x04
#define FLASH_RDID 0x9F
#define FLASH_RDSR 0x05
#define FLASH_WRSR 0x01
#define FLASH_READ 0x03
#define FLASH_FAST_READ 0x0B
#define FLASH_PP 0x02
#define FLASH_SE 0xD8
#define FLASH_BE 0xC7
/* SDB filesystem header. Fixed for the time being, the final version should simply use libsdbfs. */
const uint8_t sdb_header[] =
{ 0x53, 0x44, 0x42, 0x2d, 0x00, 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00,
0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0xc0, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0xce, 0x42, 0x00, 0x00, 0x5f, 0xec, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
0x00, 0x00, 0x2e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4f, 0xff,
0xff, 0x46, 0x69, 0x6c, 0x65, 0x44, 0x61, 0x74, 0x61, 0x61, 0x66, 0x70, 0x67, 0x00, 0x00,
0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x61, 0x66, 0x70, 0x67, 0x61, 0x2e, 0x62, 0x69, 0x6e,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x05, 0x33, 0x93, 0x46, 0x69, 0x6c, 0x65, 0x44, 0x61, 0x74, 0x61, 0x73, 0x66,
0x70, 0x67, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x73, 0x66, 0x70, 0x67, 0x61,
0x2e, 0x62, 0x69, 0x6e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01 };
struct vme_mapping map;
void *vme_va;
void release_vme()
{
vme_unmap(&map, 1);
}
void init_vme(int slot)
{
memset(&map, 0, sizeof(struct vme_mapping));
map.am = 0x2f;
map.data_width = 32;
map.sizel = 0x1000;
map.vme_addrl = slot * 0x80000 + BOOTLOADER_BASE;
if ((vme_va = vme_map(&map, 1)) == NULL) {
fprintf(stderr, "Could not map VME CSR space at 0x%08x\n",
map.vme_addrl);
exit(1);
}
atexit(release_vme);
}
static void csr_writel(uint32_t data, uint32_t addr)
{
*(volatile uint32_t *)(vme_va + addr) = htonl(data);
}
static uint32_t csr_readl(uint32_t addr)
{
return ntohl(*(volatile uint32_t *)(vme_va + addr));
}
void enter_bootloader()
{
int i = 0;
const uint32_t boot_seq[8] =
{ 0xde, 0xad, 0xbe, 0xef, 0xca, 0xfe, 0xba, 0xbe };
/* magic sequence: unlock bootloader mode, disable application FPGA */
for (i = 0; i < 8; i++)
csr_writel(boot_seq[i], SXLDR_REG_BTRIGR);
if (csr_readl(SXLDR_REG_IDR) != 0x53564543) { /* "SVEC" in hex */
fprintf(stderr,
"The bootloader is not responding. Are you sure the slot you've\
specified hosts a SVEC card? Is the SVEC's System FPGA programmer (the \"SFPGA\
Done\" LED next to the fuses should be on).\n");
exit(-1);
}
uint32_t cr = csr_readl(SXLDR_REG_CSR);
if (SXLDR_CSR_VERSION_R(cr) != BOOTLOADER_VERSION) {
fprintf(stderr,
"The bootloader is too old. Please update it according to the instructions at:\
http://www.ohwr.org/projects/svec/documents/XXX.\n");
exit(-1);
}
}
void spi_cs(int cs)
{
csr_writel(cs ? SXLDR_FAR_CS : 0, SXLDR_REG_FAR);
usleep(1);
}
uint8_t spi_read8()
{
uint32_t far;
csr_writel(SXLDR_FAR_XFER | SXLDR_FAR_DATA_W(0xff) | SXLDR_FAR_CS,
SXLDR_REG_FAR);
do {
far = csr_readl(SXLDR_REG_FAR);
} while (!(far & SXLDR_FAR_READY));
return SXLDR_FAR_DATA_R(far);
}
void spi_write8(uint8_t data)
{
uint32_t far;
csr_writel(SXLDR_FAR_XFER | SXLDR_FAR_DATA_W(data) | SXLDR_FAR_CS,
SXLDR_REG_FAR);
do {
far = csr_readl(SXLDR_REG_FAR);
} while (!(far & SXLDR_FAR_READY));
}
uint32_t flash_read_id()
{
uint32_t val = 0;
/* make sure the flash is in known state (idle) */
spi_cs(0);
usleep(10);
spi_cs(1);
usleep(10);
spi_cs(1);
spi_write8(FLASH_RDID);
val = (spi_read8() << 16);
val += (spi_read8() << 8);
val += spi_read8();
spi_cs(0);
return val;
}
static void flash_wait_completion()
{
int not_done = 1;
while (not_done) {
spi_cs(1);
spi_write8(FLASH_RDSR); /* Read Status register */
uint8_t stat = spi_read8();
not_done = (stat & 0x01);
spi_cs(0);
}
}
void flash_erase_sector(uint32_t addr)
{
spi_cs(1);
spi_write8(FLASH_SE);
spi_write8((addr >> 16) & 0xff);
spi_write8((addr >> 8) & 0xff);
spi_write8((addr >> 0) & 0xff);
spi_cs(0);
flash_wait_completion();
}
void flash_write_enable()
{
spi_cs(1);
spi_write8(FLASH_WREN);
spi_cs(0);
}
void flash_program_page(uint32_t addr, const uint8_t * data, int size)
{
int i;
spi_cs(1);
spi_write8(FLASH_PP); /* Page Program */
spi_write8((addr >> 16) & 0x00ff); /* Address to start writing (MSB) */
spi_write8((addr >> 8) & 0x00ff); /* Address to start writing */
spi_write8(addr & 0x00ff); /* Address to start writing (LSB) */
for (i = 0; i < size; i++)
spi_write8(data[i]);
spi_cs(0);
flash_wait_completion();
}
void flash_program(uint32_t addr, const uint8_t * data, int size)
{
int n = 0;
int sector_map[FLASH_SIZE / FLASH_SECTOR_SIZE];
memset(sector_map, 0, sizeof(sector_map));
const uint8_t *p = data;
while (n < size) {
int plen = (size > FLASH_PAGE_SIZE ? FLASH_PAGE_SIZE : size);
int sector = ((addr + n) / FLASH_SECTOR_SIZE);
if (!sector_map[sector]) {
flash_write_enable();
flash_erase_sector(addr + n);
sector_map[sector] = 1;
}
flash_write_enable();
flash_program_page(addr + n, data + n, plen);
fprintf(stderr, "Programming page %d/%d. \r",
n / FLASH_PAGE_SIZE,
(size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE - 1);
n += plen;
}
spi_cs(1);
spi_write8(FLASH_READ);
spi_write8((addr >> 16) & 0xff);
spi_write8((addr >> 8) & 0xff);
spi_write8((addr >> 0) & 0xff);
fprintf(stderr, "\nVerification...\n");
for (n = 0, p = data; n < size; p++, n++) {
uint8_t d = spi_read8();
if (d != *p) {
fprintf(stderr,
"Verification failed at offset 0x%06x (is: 0x%02x, should be: 0x%02x)\n.",
addr + n, d, *p);
spi_cs(1);
exit(-1);
}
}
spi_cs(1);
}
int main(int argc, char *argv[])
{
FILE *f;
void *buf;
uint32_t size;
int slot;
if (argc < 3) {
printf("usage: %s slot bitstream.bin\n", argv[0]);
return -1;
}
printf("Programming the Application FPGA flash with bitstream %s.\n",
argv[2]);
f = fopen(argv[2], "rb");
if (!f) {
perror("fopen()");
return -1;
}
fseek(f, 0, SEEK_END);
size = ftell(f);
rewind(f);
buf = malloc(size);
fread(buf, 1, size, f);
fclose(f);
slot = atoi(argv[1]);
init_vme(slot);
enter_bootloader();
if (flash_read_id() != ID_M25P128) {
fprintf(stderr, "Flash memory ID invalid.\n");
exit(-1);
}
flash_program(BOOTLOADER_BITSTREAM_BASE, buf, size);
flash_program(BOOTLOADER_SDB_BASE, sdb_header, sizeof(sdb_header));
free(buf);
printf("Programming OK.\n");
return 0;
}
/*
Register definitions for slave core: SVEC FPGA loader
* File : sxldr_regs.h
* Author : auto-generated by wbgen2 from svec_xloader_wb.wb
* Created : Mon Sep 2 10:21:20 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE svec_xloader_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_SVEC_XLOADER_WB_WB
#define __WBGEN2_REGDEFS_SVEC_XLOADER_WB_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control/status register */
/* definitions for field: Start configuration in reg: Control/status register */
#define SXLDR_CSR_START WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Configuration done in reg: Control/status register */
#define SXLDR_CSR_DONE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Configuration error in reg: Control/status register */
#define SXLDR_CSR_ERROR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Loader busy in reg: Control/status register */
#define SXLDR_CSR_BUSY WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Byte order select in reg: Control/status register */
#define SXLDR_CSR_MSBF WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Software resest in reg: Control/status register */
#define SXLDR_CSR_SWRST WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Exit bootloader mode in reg: Control/status register */
#define SXLDR_CSR_EXIT WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Serial clock divider in reg: Control/status register */
#define SXLDR_CSR_CLKDIV_MASK WBGEN2_GEN_MASK(8, 6)
#define SXLDR_CSR_CLKDIV_SHIFT 8
#define SXLDR_CSR_CLKDIV_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define SXLDR_CSR_CLKDIV_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Bootloader version in reg: Control/status register */
#define SXLDR_CSR_VERSION_MASK WBGEN2_GEN_MASK(14, 8)
#define SXLDR_CSR_VERSION_SHIFT 14
#define SXLDR_CSR_VERSION_W(value) WBGEN2_GEN_WRITE(value, 14, 8)
#define SXLDR_CSR_VERSION_R(reg) WBGEN2_GEN_READ(reg, 14, 8)
/* definitions for register: Bootloader Trigger Register */
/* definitions for register: Flash Access Register */
/* definitions for field: SPI Data in reg: Flash Access Register */
#define SXLDR_FAR_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define SXLDR_FAR_DATA_SHIFT 0
#define SXLDR_FAR_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define SXLDR_FAR_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for field: SPI Start Transfer in reg: Flash Access Register */
#define SXLDR_FAR_XFER WBGEN2_GEN_MASK(8, 1)
/* definitions for field: SPI Ready in reg: Flash Access Register */
#define SXLDR_FAR_READY WBGEN2_GEN_MASK(9, 1)
/* definitions for field: SPI Chip Select in reg: Flash Access Register */
#define SXLDR_FAR_CS WBGEN2_GEN_MASK(10, 1)
/* definitions for register: ID Register */
/* definitions for register: FIFO 'Bitstream FIFO' data input register 0 */
/* definitions for field: Entry size in reg: FIFO 'Bitstream FIFO' data input register 0 */
#define SXLDR_FIFO_R0_XSIZE_MASK WBGEN2_GEN_MASK(0, 2)
#define SXLDR_FIFO_R0_XSIZE_SHIFT 0
#define SXLDR_FIFO_R0_XSIZE_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define SXLDR_FIFO_R0_XSIZE_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Last xfer in reg: FIFO 'Bitstream FIFO' data input register 0 */
#define SXLDR_FIFO_R0_XLAST WBGEN2_GEN_MASK(2, 1)
/* definitions for register: FIFO 'Bitstream FIFO' data input register 1 */
/* definitions for field: Data in reg: FIFO 'Bitstream FIFO' data input register 1 */
#define SXLDR_FIFO_R1_XDATA_MASK WBGEN2_GEN_MASK(0, 32)
#define SXLDR_FIFO_R1_XDATA_SHIFT 0
#define SXLDR_FIFO_R1_XDATA_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define SXLDR_FIFO_R1_XDATA_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Bitstream FIFO' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Bitstream FIFO' control/status register */
#define SXLDR_FIFO_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'Bitstream FIFO' control/status register */
#define SXLDR_FIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO clear in reg: FIFO 'Bitstream FIFO' control/status register */
#define SXLDR_FIFO_CSR_CLEAR_BUS WBGEN2_GEN_MASK(18, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Bitstream FIFO' control/status register */
#define SXLDR_FIFO_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
#define SXLDR_FIFO_CSR_USEDW_SHIFT 0
#define SXLDR_FIFO_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define SXLDR_FIFO_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* [0x0]: REG Control/status register */
#define SXLDR_REG_CSR 0x00000000
/* [0x4]: REG Bootloader Trigger Register */
#define SXLDR_REG_BTRIGR 0x00000004
/* [0x8]: REG Flash Access Register */
#define SXLDR_REG_FAR 0x00000008
/* [0xc]: REG ID Register */
#define SXLDR_REG_IDR 0x0000000c
/* [0x10]: REG FIFO 'Bitstream FIFO' data input register 0 */
#define SXLDR_REG_FIFO_R0 0x00000010
/* [0x14]: REG FIFO 'Bitstream FIFO' data input register 1 */
#define SXLDR_REG_FIFO_R1 0x00000014
/* [0x18]: REG FIFO 'Bitstream FIFO' control/status register */
#define SXLDR_REG_FIFO_CSR 0x00000018
#endif
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