Commit cb16feb6 authored by Federico Vaga's avatar Federico Vaga

sw: replace loader retry with a 1ms timeout

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent df883e77
......@@ -32,6 +32,8 @@
#include <linux/fpga/fpga-mgr.h>
#include <vmebus.h>
#include "asm/processor.h"
#include "linux/jiffies.h"
#include "svec.h"
#include "svec-compat.h"
#include "hw/xloader_regs.h"
......@@ -317,19 +319,26 @@ static int svec_fpga_write_word(struct fpga_manager *mgr,
void *loader_addr = vdev->map_cr.kernel_va + SVEC_BASE_LOADER;
uint32_t xldr_fifo_r0; /* Bitstream data input control register */
uint32_t xldr_fifo_r1; /* Bitstream data input register */
int rv, try = 10000;
int rv;
unsigned long j;
if (size <= 0 || size >= 5)
return -EINVAL;
xldr_fifo_r0 = ((size - 1) & 0x3) | (is_last ? XLDR_FIFO_R0_XLAST : 0);
xldr_fifo_r1 = htonl(word);
j = jiffies + msecs_to_jiffies(1);
do {
rv = ioread32be(loader_addr + XLDR_REG_FIFO_CSR);
} while (rv & XLDR_FIFO_CSR_FULL && --try >= 0);
if (!(rv & XLDR_FIFO_CSR_FULL))
break;
cpu_relax();
} while (!time_after(jiffies, j));
if (rv & XLDR_FIFO_CSR_FULL)
if (rv & XLDR_FIFO_CSR_FULL) {
dev_dbg(&mgr->dev, "FIFO full {csr: 0x%08x}\n", rv);
return -EBUSY; /* bootloader busy */
}
iowrite32be(xldr_fifo_r0, loader_addr + XLDR_REG_FIFO_R0);
iowrite32be(xldr_fifo_r1, loader_addr + XLDR_REG_FIFO_R1);
......
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