Commit c829896c authored by Tristan Gingold's avatar Tristan Gingold

Fix minor style issues.

parent 49be322c
......@@ -7,7 +7,7 @@
-- Author(s) : Tristan Gingold <tristan.gingold@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-09-19
-- Last update: 2017-10-02
-- Last update: 2017-10-09
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the test design .
......@@ -230,7 +230,7 @@ begin -- architecture top
-------------------------------------------------------------------------------
-- Clock distribution/PLL and reset
-- Clock distribution/PLL and reset
-------------------------------------------------------------------------------
-- Input is 20Mhz
......@@ -256,7 +256,7 @@ begin -- architecture top
port map (
CLKFBOUT => pllout_clk_fb_sys,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open, --pllout_clk_sys,
CLKOUT1 => open, -- pllout_clk_sys,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
......@@ -336,9 +336,12 @@ begin -- architecture top
vme_ga <= vme_gap_i & vme_ga_i;
-- VME tri-state buffers
vme_data_b <= vme_data_b_out when vme_data_dir_int = '1' else (others => 'Z');
vme_addr_b <= vme_addr_b_out when vme_addr_dir_int = '1' else (others => 'Z');
vme_lword_n_b <= vme_lword_n_b_out when vme_addr_dir_int = '1' else 'Z';
vme_data_b <= vme_data_b_out when vme_data_dir_int = '1'
else (others => 'Z');
vme_addr_b <= vme_addr_b_out when vme_addr_dir_int = '1'
else (others => 'Z');
vme_lword_n_b <= vme_lword_n_b_out when vme_addr_dir_int = '1'
else 'Z';
vme_addr_dir_o <= vme_addr_dir_int;
vme_data_dir_o <= vme_data_dir_int;
......
......@@ -28,7 +28,7 @@
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
......@@ -61,7 +61,7 @@ architecture rtl of vmecore_test is
-- 0x3000: pattern ram (0x1000 * 4B)
signal counter : unsigned(31 downto 0);
signal leds : std_logic_vector(15 downto 0);
signal last_trans : std_logic_vector (20 downto 0);
signal nbr_read : unsigned (15 downto 0);
......@@ -69,7 +69,7 @@ architecture rtl of vmecore_test is
signal nbr_write_errors: unsigned (31 downto 0);
signal pattern : std_logic_vector (31 downto 0);
type sram_type is array (0 to 16#1ff#) of std_logic_vector(31 downto 0);
signal sram: sram_type;
begin
......@@ -86,7 +86,7 @@ begin
slave_o.ack <= '0';
slave_o.stall <= '0';
slave_o.err <= '0';
if rst_n_i = '0' then
counter <= (others => '0');
leds <= (others => '0');
......
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