Skip to content

S
Simple VME FMC Carrier SVEC
Commit be55889a authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

svec7_base_wr: apply final PCB FPGA pinout

parent dfd58450
Hide whitespace changes
Inline Side-by-side
Showing with 86 additions and 70 deletions
hdl/rtl/svec7/svec7_base_wr.vhd
View file @ be55889a
......@@ -88,9 +88,12 @@ entity svec7_base_wr is
clk_20m_vcxo_i : in std_logic := '0';
-- 125 MHz GTX reference
clk_125m_gtx_n_i : in std_logic := '0';
clk_125m_gtx_p_i : in std_logic := '0';
clk_125m_gtx_115_n_i : in std_logic := '0';
clk_125m_gtx_115_p_i : in std_logic := '0';
-- 125 MHz GTX reference
clk_125m_gtx_116_n_i : in std_logic := '0';
clk_125m_gtx_116_p_i : in std_logic := '0';
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_AUX_CLKS-1 downto 0) := (others => '0');
......@@ -106,6 +109,9 @@ entity svec7_base_wr is
vme_sysreset_n_i : in std_logic;
clk_125m_gtx_115_o : out std_logic;
clk_125m_gtx_116_o : out std_logic;
sfpga_clk_p_o : out std_logic;
sfpga_clk_n_o : out std_logic;
sfpga_rx_i : in std_logic_vector(4 downto 0);
......@@ -135,17 +141,26 @@ entity svec7_base_wr is
carrier_scl_b : inout std_logic;
carrier_sda_b : inout std_logic;
ddr3_spd_scl_b : inout std_logic;
ddr3_spd_sda_b : inout std_logic;
ddr_spd_scl_b : inout std_logic;
ddr_spd_sda_b : inout std_logic;
-- I/O Expander for the slow pins
ps_fmc_2v5_en_o : out std_logic;
ps_fmc_3v3_en_o : out std_logic;
ps_fmc_vadj_en_o : out std_logic;
ioexp_clk_inh_o : out std_logic;
ioexp_sclk_o : out std_logic;
ioexp_rclk_o : out std_logic;
ioexp_rclk_power_o : out std_logic;
ioexp_sh_ld_o : out std_logic;
ioexp_d_o : out std_logic;
ioexp_reset_o : out std_logic;
ioexp_d_i : in std_logic;
---------------------------------------------------------------------------
---------------------------------------------------------------x------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
......@@ -164,8 +179,6 @@ entity svec7_base_wr is
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll20dac_din_o : out std_logic;
pll20dac_sclk_o : out std_logic;
pll20dac_sync_n_o : out std_logic;
......@@ -193,21 +206,21 @@ entity svec7_base_wr is
-- DDR
------------------------------------------
ddr3_addr : out std_logic_vector(15 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_cas_n : out std_logic;
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ddr3_ras_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_we_n : out std_logic;
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr_a_o : out std_logic_vector(15 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic_vector(0 downto 0);
ddr_dq_b : inout std_logic_vector(63 downto 0);
ddr_dqs_n_b : inout std_logic_vector(7 downto 0);
ddr_dqs_p_b : inout std_logic_vector(7 downto 0);
ddr_odt_o : out std_logic_vector(0 downto 0);
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_dm_o : out std_logic_vector(7 downto 0);
ddr_we_n_o : out std_logic;
ddr_cs_n_o : out std_logic_vector(0 downto 0);
......@@ -225,6 +238,7 @@ entity svec7_base_wr is
-- Clocks and reset.
clk_sys_62m5_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
clk_ref_62m5_o : out std_logic;
rst_ref_62m5_n_o : out std_logic;
......@@ -297,7 +311,6 @@ architecture top of svec7_base_wr is
others => c_AUXPLL_CFG_DEFAULT);
signal clk_sys_62m5 : std_logic; -- 62.5Mhz
signal clk_sys_125m : std_logic; -- 62.5Mhz
signal clk_ddr_200m : std_logic;
signal clk_pll_aux : std_logic_vector(3 downto 0);
......@@ -309,18 +322,6 @@ architecture top of svec7_base_wr is
signal vme_wb_out : t_wishbone_master_out;
signal vme_wb_in : t_wishbone_master_in;
signal vme_wb_125m_out : t_wishbone_master_out;
signal vme_wb_125m_in : t_wishbone_master_in;
-- VME
signal vme_data_b_out : std_logic_vector(31 downto 0);
signal vme_addr_b_out : std_logic_vector(31 downto 1);
signal vme_lword_n_b_out : std_logic;
signal vme_data_dir_int : std_logic;
signal vme_addr_dir_int : std_logic;
signal vme_ga : std_logic_vector(5 downto 0);
signal vme_berr_n : std_logic;
signal vme_irq_n : std_logic_vector(7 downto 1);
-- The wishbone bus to the carrier part.
signal carrier_wb_out : t_wishbone_slave_out;
......@@ -374,7 +375,6 @@ architecture top of svec7_base_wr is
-- clock and reset
signal rst_sys_62m5_n : std_logic;
signal rst_sys_125m_n : std_logic;
signal rst_ref_62m5_n : std_logic;
signal clk_ref_62m5 : std_logic;
signal rst_ddr_200m_n : std_logic;
......@@ -416,6 +416,19 @@ architecture top of svec7_base_wr is
begin -- architecture top
-- Dedicated GTX clock.
cmp_gtp_dedicated_clk_116 : IBUFDS_GTE2
generic map(
CLKCM_CFG => true,
CLKRCV_TRST => true,
CLKSWING_CFG => "11")
port map (
O => clk_125m_gtx_116_o,
ODIV2 => open,
CEB => '0',
I => clk_125m_gtx_116_p_i,
IB => clk_125m_gtx_116_n_i);
------------------------------------------------------------------------------
-- VME interface
------------------------------------------------------------------------------
......@@ -466,20 +479,6 @@ begin -- architecture top
int_i => irq_master);
-- u_ClockBridge:xwb_clock_bridge
-- generic map (
-- g_SLAVE_PORT_WB_MODE => PIPELINED,
-- g_MASTER_PORT_WB_MODE => PIPELINED,
-- g_SIZE => 256)
-- port map (
-- slave_clk_i => clk_sys_125m,
-- slave_rst_n_i => rst_sys_125m_n,
-- slave_i => vme_wb_125m_out,
-- slave_o => vme_wb_125m_in,
-- master_clk_i => clk_sys_62m5,
-- master_rst_n_i => rst_sys_125m_n,
-- master_i => vme_wb_in,
-- master_o => vme_wb_out);
-- Mini-crossbar from vme to carrier and application bus.
inst_split: entity work.xwb_split
......@@ -761,19 +760,17 @@ begin -- architecture top
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtx_n_i => clk_125m_gtx_n_i,
clk_125m_gtx_p_i => clk_125m_gtx_p_i,
clk_125m_gtx_n_i => clk_125m_gtx_115_n_i,
clk_125m_gtx_p_i => clk_125m_gtx_115_p_i,
clk_aux_i => clk_aux_i,
clk_10m_ext_i => clk_10m_ext_i,
pps_ext_i => pps_ext_i,
clk_sys_62m5_o => clk_sys_62m5,
clk_sys_125m_o => clk_sys_125m,
clk_ref_62m5_o => clk_ref_62m5,
clk_pll_aux_o => clk_pll_aux,
clk_dmtd_62m5_o => clk_dmtd_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_sys_125m_n_o => rst_sys_125m_n,
rst_ref_62m5_n_o => rst_ref_62m5_n,
rst_pll_aux_n_o => rst_pll_aux_n,
......@@ -1075,25 +1072,26 @@ begin -- architecture top
--fixme
ddr_sys_rst <= not rst_ddr_200m_n;
ddr_axi_aresetn <= rst_ddr_200m_n;
ddr3_mmcm_locked <= '1'; --not ddr_sys_rst;
cmp_mig : entity work.svec7_ddr_controller_mig
port map
(
ddr3_dq => ddr3_dq,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_addr => ddr3_addr(15 downto 0),
ddr3_ba=> ddr3_ba,
ddr3_ras_n=> ddr3_ras_n,
ddr3_cas_n=> ddr3_cas_n,
ddr3_we_n=> ddr3_we_n,
ddr3_reset_n=> ddr3_reset_n,
ddr3_ck_p=> ddr3_ck_p(0),
ddr3_ck_n=> ddr3_ck_n(0),
ddr3_cke=> ddr3_cke(0),
ddr3_cs_n=> ddr3_cs_n(0),
ddr3_dm=> ddr3_dm,
ddr3_odt=> ddr3_odt(0),
ddr3_dq => ddr_dq_b,
ddr3_dqs_n => ddr_dqs_n_b,
ddr3_dqs_p => ddr_dqs_p_b,
ddr3_addr => ddr_a_o(15 downto 0),
ddr3_ba=> ddr_ba_o,
ddr3_ras_n=> ddr_ras_n_o,
ddr3_cas_n=> ddr_cas_n_o,
ddr3_we_n=> ddr_we_n_o,
ddr3_reset_n=> ddr_reset_n_o,
ddr3_ck_p=> ddr_ck_p_o,
ddr3_ck_n=> ddr_ck_n_o,
ddr3_cke=> ddr_cke_o,
ddr3_cs_n=> ddr_cs_n_o,
ddr3_dm=> ddr_dm_o,
ddr3_odt=> ddr_odt_o,
sys_clk_i => clk_ddr_200m,
clk_ref_i => clk_ddr_200m,
......@@ -1168,4 +1166,22 @@ begin -- architecture top
clk_dmtd_62m5_o <= clk_dmtd_62m5;
-- fixme : implement
ps_fmc_2v5_en_o <= '1';
ps_fmc_3v3_en_o <= '1';
ps_fmc_vadj_en_o <= '1';
ioexp_clk_inh_o <= '0';
ioexp_sclk_o <= '0';
ioexp_rclk_o <= '0';
ioexp_rclk_power_o <= '0';
ioexp_sh_ld_o <= '0';
ioexp_d_o <= '0';
ioexp_reset_o <= '0';
ddr_spd_scl_b <= '0';
ddr_spd_sda_b <= '0';
end architecture top;
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment